DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/21/2026 with regard to the rejection of claims 1-9 under 35 U.S.C. 103 have been fully considered but they are not persuasive. When applying prior art to the broadest reasonable interpretation of the claimed language, Examiner has the freedom to define certain components differently from the prior art reference so long as it does not differ from the general understanding within the art. For example, even though primary reference Liao defines surface 211 as a “first surface” in Figure 1, that does not prevent the Examiner from defining any other surface in the prior art reference as a “first surface”. The same is true for defining surface 272 as a “first surface” in the rejection of record, even though Liao defines the same surface as a “second surface”. The rejection accordingly is deemed proper and is made FINAL.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao et al. (US-20240021640-A1 – hereinafter Liao) in view of Chen et al. (US-20250349624-A1 – hereinafter Chen).
Regarding claim 1, Liao teaches an electronic package (Fig.1 10; ¶0048), comprising:
an encapsulation layer (Fig.1 260; ¶0058) having a first surface (Fig.1 272; ¶0060) and a second surface (Fig.1 211; ¶0056) opposing the first surface (272);
a first electronic element (Fig.1 240; ¶0059) embedded in the encapsulation layer (260), wherein the first electronic element (240) has an active surface (top surface of 240) and an inactive surface (bottom surface of 240) opposing the active surface (top surface of 240), wherein the active surface (top surface of 240) has a plurality of conductors (Fig.1 241; ¶0057), and surfaces of the conductors (241) are flush with the first surface (272) of the encapsulation layer (260);
a first bonding layer (Fig.1 230 left; ¶0057) embedded in the encapsulation layer (260) and bonded on the inactive surface (bottom of 240), wherein an outer surface of the first bonding layer (230 left) is flush with the second surface (211) of the encapsulation layer (260);
a dummy die (Fig.1 250; ¶0057) embedded in the encapsulation layer (260) and spaced apart from the first electronic element (240);
a second bonding layer (Fig.1 230 right; ¶0057) embedded in the encapsulation layer (260) and bonded on the dummy die (250), wherein an outer surface of the second bonding layer (230 right) is flush with the second surface (211) of the encapsulation layer (260), wherein a thickness of the first bonding layer (230 left) is less than (Fig.1 depicts the left portion of 230 being thinner than the right portion) a thickness of the second bonding layer (230 right); and
a circuit structure (Fig.1 270; ¶0060) disposed on the first surface (272) of the encapsulation layer (260) and electrically connected to the first electronic element (240).
Liao does not teach wherein a surface of the dummy die is flush with the first surface of the encapsulation layer.
Chen teaches an electronic package (Fig.10; ¶0061 of Chen) with an encapsulant (Fig.8 82; ¶0053 of Chen) and a dummy die (Fig.10 70B; ¶0046 of Chen) where the dummy die (70B of Chen) is flush with both top and bottom surfaces of encapsulant (82 of Chen).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the dummy die of Liao (250 of Liao) to be larger and flush with the first surface of Liao (272 of Liao) as taught by Chen (Fig.10 70B of Chen) to arrive at the claimed invention. A practitioner of ordinary skill would have been motivated to make this modification for the benefit of increased heat dissipation due to a larger dummy die (¶0046 of Chen).
Regarding claim 2, the aforementioned combination of Liao in view of Chen from claim 1 teaches the electronic package of claim 1, wherein the second surface (211) of the encapsulation layer (260) is bonded with a dielectric protection layer (Fig.1 210; ¶0055), and the dielectric protection layer (210) is in contact with the first bonding layer (230 left) and the second bonding layer (230 right).
Regarding claim 3, the aforementioned combination of Liao in view of Chen from claim 1 teaches the electronic package of claim 1, further comprising a second electronic element (Fig.1 110; ¶0048) disposed on and electrically connected to the circuit structure (270).
Regarding claim 9, the aforementioned combination of Liao in view of Chen from claim 1 teaches the electronic package of claim 1, further comprising a plurality of conductive elements (Fig.1 130; ¶0048) formed on the circuit structure (270).
Claim(s) 4-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao in view of Chen, and further in view of Chen et al. (US-20250349784-A1 – hereinafter Pai).
Regarding claim 4, the aforementioned combination of Liao in view of Chen from claim 3 teaches the electronic package of claim 3.
The aforementioned combination does not teach wherein the second electronic element is a bridge element for electrically bridging the first electronic element and another electronic element electrically connected to the circuit structure via the circuit structure.
Pai teaches a bridge die (Fig.10 140; ¶0046 of Pai) for electrically bridging two electronic elements (Fig.10 50; ¶0015 of Pai), the bridge die (140 of Pai) being surrounded by an encapsulant (Fig.10 154; ¶0049) and conductive pillars (Fig.10 116; ¶0049) which are also connected to a routing layer (Fig.10 170; ¶0050) with conductive elements (Fig.10 176; ¶0054).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the second electronic elements of Liao (110 of Liao) with the bridge die (140 of Pai) and accompanying components of Pai (154, 116, 170 and 176 of Pai) so that the first electronic component (240 of Liao) and dummy die (250 of Liao) of the aforementioned combination are in a similar place as the electronic elements of Pai (50 of Pai) to arrive at the claimed invention. This substitution is obvious because different configurations of well-known components could be required for different applications.
Regarding claim 5, the aforementioned combination of Liao in view of Chen from claim 3 teaches the electronic package of claim 3.
The aforementioned combination does not teach the electronic package further comprising conductive pillars disposed on and electrically connected to the circuit structure.
Pai teaches a bridge die (Fig.10 140; ¶0046 of Pai) for electrically bridging two electronic elements (Fig.10 50; ¶0015 of Pai), the bridge die (140 of Pai) being surrounded by an encapsulant (Fig.10 154; ¶0049) and conductive pillars (Fig.10 116; ¶0049) which are also connected to a routing layer (Fig.10 170; ¶0050) with conductive elements (Fig.10 176; ¶0054).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to substitute the second electronic elements of Liao (110 of Liao) with the bridge die (140 of Pai) and accompanying components of Pai (154, 116, 170 and 176 of Pai) so that the first electronic component (240 of Liao) and dummy die (250 of Liao) of the aforementioned combination are in a similar place as the electronic elements of Pai (50 of Pai) to arrive at the claimed invention. This substitution is obvious because different configurations of well-known components could be required for different applications.
Regarding claim 6, the aforementioned combination of Liao in view of Chen, and further in view of Pai from claim 5 teaches the electronic package of claim 5, further comprising a packaging layer (Fig.10 154; ¶0049 of Pai) covering the conductive pillars (116 of Pai) and the second electronic element (140 of Pai), wherein end surfaces of the conductive pillars (116 of Pai) are flush with a surface of the packaging layer (154 of Pai).
Regarding claim 7, the aforementioned combination of Liao in view of Chen, and further in view of Pai from claim 6 teaches the electronic package of claim 6, further comprising a routing structure (Fig.10 170; ¶0050 of Pai) formed on the packaging layer (154 of Pai) and electrically connected to the conductive pillars (116 of Pai).
Regarding claim 8, the aforementioned combination of Liao in view of Chen, and further in view of Pai from claim 7 teaches the electronic package of claim 7, further comprising a plurality of conductive elements (Fig.10 176; ¶0048 of Pai) formed on the routing structure (170 of Pai).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817