DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group II, species IIA, in the reply filed on 10/27/2025 is acknowledged. Claims 1-15 have been canceled. Claims 21-35 are added.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-26, 28-32 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang et al. (US 2011/0042750 A1) in view of Okagaki et al. (US 2016/0049395 A1).
Regarding claim 16, Chuang teaches a method for fabricating an IC structure (method in Figs. 14A-14C, and 20 of Chuang. Figs. 14A-14C is an alternative embodiment of Figs. 3-9), comprising:
forming an active region (74 in Fig. 14A) over a semiconductor substrate (10, as shown in Fig. 4), wherein the active region extends substantially along a first direction (left-right direction in Figs. 14A);
forming an isolation structure (STI between active regions 72 and 74 as described in [0028] of Chuang, ) around the active region; and
forming a first gate structure (70 in Fig. 14A) over the semiconductor substrate, wherein the first gate structure comprises a first gate line (lower half of 70a in Fig. 14A) and an auxiliary gate portion (70c), the first gate line extends substantially along a second direction (up-down direction in Fig. 14A) different from the first direction, and the auxiliary gate portion is over the isolation structure (as shown in Fig. 14A) and extends from a sidewall (right sidewall of 70a) of the first gate line along the first direction from a top view.
But Chuang does not teach that the active region is a semiconductor fin.
Okagaki teaches a device where active regions are semiconductor fins (F in Figs. 2-3 of Okagaki) that are separated by isolation structures (ISO in Fig. 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed active regions of Chuang as fin structures, as disclosed by Okagaki, in order to increase the device density of Chuang.
Regarding claim 17, Chuang in view of Okagaki teaches all limitations of the method of claim 16, and further comprising: forming a gate contact (119 in Fig. 20 of Chuang), wherein the gate contact has a first portion (lower left half of 119) over the first gate line (the boundary of the first gate line and auxiliary gate portion is arbitrary so it can be defined as the diagonal line from the square corner to the curve corner) and a second portion (upper right half of 119) over the auxiliary gate portion.
Regarding claim 18, Chuang in view of Okagaki teaches all limitations of the method of claim 16, and also teaches wherein the first gate line extends across the semiconductor fin (as shown in Fig. 14C of Chuang).
Regarding claim 19, Chuang in view of Okagaki teaches all limitations of the method of claim 16, and also teaches wherein forming the first gate structure is performed such that the first gate structure further comprises a second gate line (upper portion of 70b in Fig. 14A of Chuang), and the auxiliary gate portion extend from the sidewall of the first gate line along the first direction to a sidewall of the second gate line from a top view (as shown in Figs. 14A-14C of Chuang).
Regarding claim 20, Chuang in view of Okagaki teaches all limitations of the method of claim 16, and further comprising: forming a second gate structure (upper half of 70a in Fig. 14C of Chuang) over the semiconductor substrate, wherein the second gate structure is immediately adjacent to the sidewall of the first gate line (as shown in Fig. 14C of Chuang), and the auxiliary gate portion is free of contacting the second gate structure (as shown in Fig. 14C of Chuang).
Regarding claim 21, Chuang teaches a method for fabricating an IC structure (method in Figs. 14A-14C, and 20 of Chuang. Figs. 14A-14C is an alternative embodiment of Figs. 3-9), comprising:
forming an active region (74 in Fig. 14A) over a semiconductor structure (substrate 10), wherein the active region extends substantially along a first direction (left-right direction in Figs. 14A);
forming a first gate line (lower half of 70a in Fig. 14A) and a second gate line (upper half of 70b in Fig. 14A) extending substantially along a second direction (vertical up-down direction in Fig. 14A) different from the first direction from a top view; and
forming a first auxiliary gate portion (70c in Fig. 14A) connecting the first gate line to the second gate line from the top view.
But Chuang does not teach that the active region is a semiconductor fin.
Okagaki teaches a device where active regions are semiconductor fins (F in Figs. 2-3 of Okagaki) that are separated by isolation structures (ISO in Fig. 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed active regions of Chuang as fin structures, as disclosed by Okagaki, in order to increase the device density of Chuang.
Regarding claim 22, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and also teaches wherein the first auxiliary gate portion is spaced apart from the semiconductor fin along the second direction from the top view (as shown in Figs. 14A-14C of Chuang).
Regarding claim 23, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and further comprising: forming a gate contact (119 in Fig. 20 of Chuang) having a first portion (lower left half of 119) over one of the first (the boundary of the first gate line and auxiliary gate portion is arbitrary so it can be defined as the diagonal line from the square corner to the curve corner in Fig. 20 of Chuang) and second gate lines and a second portion (upper right half of 119) over the first auxiliary gate portion.
Regarding claim 24, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and also teaches wherein the first gate line extends across the semiconductor fin (as shown in Fig. 20 of Chuang), and the second gate line does not extend across the semiconductor fin (as shown in Fig. 14A of Chuang).
Regarding claim 25, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and further comprising: forming a third gate line (lower half of 70b in Fig. 14A) extending substantially along the second direction and across the semiconductor fin, wherein the third gate line is aligned with the second gate line along the second direction (as shown in Fig. 14A of Chuang).
Regarding claim 26, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and further comprising: forming a fourth gate line (upper half of 70a in Fig. 14A) extending substantially along the second direction, and the first auxiliary gate portion connects the fourth gate line to the first and second gate lines (as shown in Fig. 14A).
Regarding claim 28, Chuang in view of Okagaki teaches all limitations of the method of claim 21, and also teaches wherein one of the first and second gate lines extends beyond opposite sides of the first auxiliary gate portion along the second direction (as shown in Fig. 14A of Chuang).
Regarding claim 29, Chuang teaches a method for fabricating an IC structure (method in Figs. 14A-14C, and 20 of Chuang. Figs. 14A-14C is an alternative embodiment of Figs. 3-9), comprising:
forming an active region (74 in Fig. 14A) over a semiconductor structure (10, as shown in Fig. 4), wherein the active region extends substantially along a first direction (left-right direction in Figs. 14A);
forming a first gate line (lower half of 70a in Fig. 14A) and a second gate line (upper half of 70b in Fig. 14A), wherein the first and second gate lines extend substantially along a second direction (up-down direction in Figs. 14A) different from the first direction, and the second gate line is adjacent to a first sidewall (right sidewall of 70a) of the first gate line; and
forming a first auxiliary gate portion (70c) extending from the first sidewall of the first gate line along the first direction from a top view (as shown in Fig. 14A), wherein the first auxiliary gate portion connects the second gate line (as shown in Fig. 14A).
But Chuang does not teach that the active region is a semiconductor fin.
Okagaki teaches a device where active regions are semiconductor fins (F in Figs. 2-3 of Okagaki) that are separated by isolation structures (ISO in Fig. 3).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed active regions of Chuang as fin structures, as disclosed by Okagaki, in order to increase the device density of Chuang.
Regarding claim 30, Chuang in view of Okagaki teaches all limitations of the method of claim 29, and further comprising: forming an isolation structure (STI between active regions 72 and 74 as described in [0028] of Chuang) surrounding the semiconductor fin, and the first auxiliary gate portion is over the isolation structure (as shown in Fig. 14A of Chuang).
Regarding claim 31, Chuang in view of Okagaki teaches all limitations of the method of claim 29, and also teaches wherein the first gate line extends across the semiconductor fin (as shown in Fig. 14A of Chuang), and the first auxiliary gate portion is spaced apart from the semiconductor fin along the second direction from a top view (as shown in Fig. 14A of Chuang).
Regarding claim 32, Chuang in view of Okagaki teaches all limitations of the method of claim 29, and further comprising: forming a gate contact (119 in Fig. 20 of Chuang) having a first portion (lower left half of 119) over the first gate line (the boundary of the first gate line and auxiliary gate portion is arbitrary so it can be defined as the diagonal line from the square corner to the curve corner) and a second portion (upper right half of 119) over the first auxiliary gate portion.
Claims 27, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang in view of Okagaki, as applied in claim 21, and further in view of Tesson et al. (US 2018/0211882 A1).
Regarding claim 27, Chuang in view of Okagaki teaches all limitations of the method of claim 21, but does not teach the method further comprising: forming a second auxiliary gate portion connecting the first gate line to the second gate line.
Tesson teaches a device where the gate structure (14, and 18 in Fig. 4 of Tesson) across multiple transistor cells form a grid-like structures. The grid-like gate structure includes first and second gate lines (14) that are connected to each other by first and second auxiliary gate portions (portions of 10 connecting the two gate lines 14 together).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the grid-like gate structures in situation when the application like Tesson’s device requires it.
Regarding claim 33, Chuang in view of Okagaki teaches all limitations of the method of claim 29, but does not teach the method further comprising: forming a second auxiliary gate portion connecting the second gate line to a fourth gate line, wherein the first auxiliary gate portion connects the first gate line to the second gate line, and the second auxiliary gate portion is misaligned with the first auxiliary gate portion along the first direction.
Tesson teaches a device where the gate structure (14, and 18 in Fig. 3 of Tesson) across multiple transistor cells form a grid-like structures. The grid-like gate structure includes first and second gate lines (14) that are connected to each other by first and second auxiliary gate portions (portions of 10 connecting the two gate lines 14 together).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the grid-like gate structures in situation when the application like Tesson’s device requires it.
As incorporated, the upper horizontal portion of 10 connecting the two gate lines 14 (in Fig. 3 of Tesson) is identified as the first auxiliary gate portion and the lower horizontal portion is the second auxiliary gate portion. These first and second auxiliary gate portions are misaligned with each other along the left-right direction.
Regarding claim 34, Chuang in view of Okagaki teaches all limitations of the method of claim 29, but does not teach the method further comprising: forming a second auxiliary gate portion extending from a sidewall of the second gate line along the first direction, and the second auxiliary gate portion is aligned with the first auxiliary gate portion along the first direction.
Tesson teaches a device where the gate structure (14, and 18 in Fig. 3 of Tesson) across multiple transistor cells form a grid-like structures. The grid-like gate structure includes first and second gate lines (14) that are connected to each other by first and second auxiliary gate portions (portions of 10 connecting the two gate lines 14 together).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the grid-like gate structures in situation when the application like Tesson’s device requires it.
As incorporated, the upper horizontal portion of 10 between and connecting the two gate lines 14 (in Fig. 3 of Tesson) is identified as the first auxiliary gate portion and the upper horizontal portion of 10 to the right of the right gate line 14 is the second auxiliary gate portion. As such, the first and second auxiliary gate portions are aligned with each other along the left-right direction.
Regarding claim 35, Chuang in view of Okagaki teaches all limitations of the method of claim 29, but does not teach the method further comprising: forming a third gate line extending substantially along the second direction, wherein the third gate line is immediately adjacent to a second sidewall of the first gate line, and the first auxiliary gate portion connects the first gate line to the third gate line.
Tesson teaches a device where the gate structure (14, and 18 in Fig. 3 of Tesson) across multiple transistor cells form a grid-like structures. The grid-like gate structure includes first and second gate lines (14) that are connected to each other by first and second auxiliary gate portions (portions of 10 connecting the two gate lines 14 together).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the grid-like gate structures in situation when the application like Tesson’s device requires it.
As incorporated, a vertical portion of the loop-shaped part 18 to the left of the first gate line 14 can be identified as the third gate line. If the first sidewall of the first gate line is defined as the right sidewall, the second sidewall is then the left sidewall.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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