DETAILED ACTION
This action is responsive to the application No. 18/190,893 filed on March 27, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 06/02/2026 responding to the Office action mailed on 11/14/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-11 and 16-21.
Claim Rejections - 35 USC § 112
Claims 20-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 recites the limitation “the gate portion”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 11, and 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over Unnikrishnan (US 2003/0111693) in view of Tamura (US 2024/0097028).
Regarding Claim 1, Unnikrishnan (see, e.g., Figs. 1-5), teaches an electronic device, comprising:
a silicon layer 12 having a first surface (i.e., lower surface) and a second surface (i.e., upper surface) (see, e.g., pars. 0018-0019),
an insulating layer 14 in contact with the first surface of the silicon layer 12 (see, e.g., par. 0019),
at least one transistor 10 comprising source 22, drain 24, and body 18 regions arranged in the silicon layer 12, and a gate region 20 topping the body region 18 and comprising a gate portion 34 laterally extending beyond the source 22 and drain 24 regions, the body region 18 being continued by a body contact region 26 not covered with the gate region 20, and a region of extension (see, e.g., region below 46) of the body region 18 being located under the gate portion 34 (see, e.g., pars. 0020-0021, 0027); and
the gate portion 34 being less heavily doped than the rest 36 of the gate region 20 (see, e.g., par. 0027).
Further, Unnikrishnan teaches a silicide layer 42 on top of the gate portion 34 to electrically couple undoped portion 34 to doped portion 36 of gate 20 (see e.g., par. 0027).
Unnikrishnan is silent with respect to the claim limitation that the gate portion is coupled to at least one gate contact pad, the at least one gate contact pad being positioned directly above the gate portion.
Tamura (see, e.g., Fig. 1), on the other hand, teaches that the gate portion 31 is coupled to at least one gate contact pad 44, the at least one gate contact pad 44 being positioned directly above the gate portion 44, to apply a gate potential Vg to the gate electrode 24 (see, e.g., pars. 0052, 0056).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Unnikrishnan device, the gate portion being coupled to at least one gate contact pad via a first silicide layer, the at least one gate contact pad being positioned directly above the gate portion, as taught by Tamura, to apply a gate potential Vg to the gate electrode.
Regarding Claim 2, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the gate portion 34 is non-intentionally doped.
Regarding Claim 3, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the body contact region 26 is laterally positioned next to the gate portion 34.
Regarding Claim 4, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that:
the body region 18 comprises a channel region between the source region 22 and the drain region 24; and
the gate region 20 comprises a first portion 36 topping the channel region, the gate portion 34 being a second portion of the gate region 20 continuing said first portion 36 laterally beyond said channel region.
Regarding Claim 5, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the gate portion 34 is coupled to at least one gate contact pad, preferably via a first silicide layer 42 (see, e.g., pars. 0025-0027).
Regarding Claim 6, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the body contact region 26, the source region 22, and the drain region 24 are flush with the second surface (i.e., upper surface) of the silicon layer 12.
Regarding Claim 7, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the body contact region 26 is coupled to at least one body contact pad, for example, via a second silicide layer 44 (see, e.g., par. 0025).
Regarding Claim 8, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches a first peripheral insulating trench 16, the body contact region 26 being laterally positioned between said first peripheral insulating trench 16 and the gate portion 34 (see, e.g., par. 0019).
Regarding Claim 9, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches a second peripheral insulating trench 16, the source 22 and drain 24 regions being laterally positioned between said second peripheral insulating trench 16 and the gate portion 34.
Regarding Claim 11, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches a gate insulator layer 21 between the gate region 20 and the silicon layer 12 (see, e.g., par. 0020).
Regarding Claim 16, Unnikrishnan (see, e.g., Figs. 1-5), teaches a device, comprising:
a substrate (see, e.g., par. 0027);
a silicon layer 12 on the substrate including source 22, drain 24, and body 18 regions (see, e.g., par. 0019-0021, 0027);
a body contact region 26 in the silicon layer 12, a first surface (i.e., surface of silicide layer 44) of the body contact region 26 being spaced from the substrate by a first distance (i.e., thickness of silicon layer 12 and oxide layer 14);
a gate region 20 on the silicon layer 12, a second surface (i.e., surface of silicide layer 42) of the gate region 20 being spaced from the substrate by a second distance (i.e., thickness of gate region 20, insulator layer 21 silicon layer 12 and oxide layer 14) that is greater than the first distance, a sidewall of the gate region 20 facing the body contact region 26.
the gate region 20 including a gate portion 34 laterally extending beyond the source 22 and drain 24 regions (see, e.g., pars. 0020-0021, 0027).
Further, Unnikrishnan teaches a silicide layer 42 on top of the gate portion 34 to electrically couple undoped portion 34 to doped portion 36 of gate 20 (see e.g., par. 0027).
Unnikrishnan is silent with respect to the claim limitation that the gate portion is coupled to at least one gate contact pad, the at least one gate contact pad being positioned directly above the gate portion.
Tamura (see, e.g., Fig. 1), on the other hand, teaches that the gate portion 31 is coupled to at least one gate contact pad 44, the at least one gate contact pad 44 being positioned directly above the gate portion 44, to apply a gate potential Vg to the gate electrode 24 (see, e.g., pars. 0052, 0056).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Unnikrishnan device, the gate portion being coupled to at least one gate contact pad via a first silicide layer, the at least one gate contact pad being positioned directly above the gate portion, as taught by Tamura, to apply a gate potential Vg to the gate electrode.
Regarding Claim 17, Unnikrishnan and Tamura teach all aspects of claim 16. Unnikrishnan (see, e.g., Figs. 1-5), teaches that a first contact is coupled to the first surface 44 and a second contact is coupled to the second surface 42 (see, e.g., pars. 0025-0027).
Regarding Claim 18, Unnikrishnan and Tamura teach all aspects of claim 17. Unnikrishnan (see, e.g., Figs. 1-5), teaches a gate insulator 21 only between the gate region 20 and the substrate (see, e.g., par. 0020).
Regarding Claim 19, Unnikrishnan and Tamura teach all aspects of claim 18. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the first surface includes a silicide layer 44 that abuts the gate insulator 21 (see, e.g., par. 0025).
Regarding Claim 20, Unnikrishnan (see, e.g., Figs. 1-5), teaches a device, comprising:
a substrate (see, e.g., par. 0027);
a silicon layer 12 including a first surface (i.e., lower surface) (see, e.g., par. 0019);
an insulating layer 14 in contact with the first surface (see, e.g., par. 0019); and
a transistor 10 including a source region 22 in the silicon layer 12, a drain region 24 in the silicon layer 12, a body region 18 in the silicon layer 12, and a gate region 20 on the silicon layer 12,
wherein:
the body region 18 includes a channel region (i.e., region between the source region 22 and the drain region 24), the gate region 20 including a first portion 36 topping the channel region and a second portion 34 continuing the first portion 36 laterally beyond the source 22, drain 24 and channel regions (see, e.g., pars. 0020-0021),
the body region 18 including a body contact region 26 not covered with the gate region 20, and a region of extension (see, e.g., region below 46) of the body region 18 being located under the second portion 34 of the gate region 20 (see, e.g., pars. 0020-0021, 0027).
Further, Unnikrishnan teaches a silicide layer 42 on top of the gate portion 34 to electrically couple undoped portion 34 to doped portion 36 of gate 20 (see e.g., par. 0027).
Unnikrishnan is silent with respect to the claim limitation that the gate portion is coupled to at least one gate contact pad, the at least one gate contact pad being positioned directly above the gate portion.
Tamura (see, e.g., Fig. 1), on the other hand, teaches that the gate portion 31 is coupled to at least one gate contact pad 44, the at least one gate contact pad 44 being positioned directly above the gate portion 44, to apply a gate potential Vg to the gate electrode 24 (see, e.g., pars. 0052, 0056).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Unnikrishnan device, the gate portion being coupled to at least one gate contact pad via a first silicide layer, the at least one gate contact pad being positioned directly above the gate portion, as taught by Tamura, to apply a gate potential Vg to the gate electrode.
Regarding Claim 21, Unnikrishnan and Tamura teach all aspects of claim 20. Unnikrishnan (see, e.g., Figs. 1-5), teaches a first contact 44 coupled to the body contact region 26 at a first distance from the substrate (i.e., thickness of silicon layer 12 and oxide layer 14) and a second contact 42 coupled to the gate region 20 at a second distance from the substrate (i.e., thickness of gate region 20, insulator layer 21 silicon layer 12 and oxide layer 14), the first distance being smaller than the second distance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Unnikrishnan (US 2003/0111693) in view of Tamura (US 2024/0097028) and further in view of Liu (US 2023/0018629).
Regarding Claim 10, Unnikrishnan and Tamura teach all aspects of claim 1. Unnikrishnan (see, e.g., Figs. 1-5), teaches that the at least one transistor 10 is a transistor on a structure of silicon-on-insulator type comprising the silicon layer 12, the insulating layer 14, and a substrate topped with said insulating layer 14 (see, e.g., pars. 0018-0019).
Unnikrishnan is silent with respect to the claim limitation that the structure being for example a structure of partially depleted silicon on insulator type.
Liu (see, e.g., Fig. 1), on the other hand, teaches that when radio frequency (RF) switching devices are disposed over/within a moderately thin semiconductor layer (e.g., partially-depleted semiconductor-on-insulator (PDSOI) substrate), they benefit from a low capacitance when the RF switching devices are in an off state (e.g., COFF) (see, e.g., pars. 0017).
It would have been obvious to one of ordinary skill in the art at the time of filing to include a structure of partially depleted silicon on insulator type in Unnikrishnan’s/Tamura’s device, as taught by Liu, to benefit from a low capacitance when the RF switching devices are in an off state (e.g., COFF).
Response to Arguments
Applicant’s arguments filed on 06/02/2026 with respect to the rejection of claims 1, 16, and 20 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:30 PM.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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