Prosecution Insights
Last updated: April 19, 2026
Application No. 18/190,897

MOS TRANSISTOR ON SOI STRUCTURE

Non-Final OA §102§103§112
Filed
Mar 27, 2023
Examiner
BOOTH, RICHARD A
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 4m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
878 granted / 1029 resolved
+17.3% vs TC avg
Moderate +8% lift
Without
With
+8.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
35 currently pending
Career history
1064
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
56.2%
+16.2% vs TC avg
§102
29.9%
-10.1% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1029 resolved cases

Office Action

§102 §103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of group I in the reply filed on 08/15/25 is acknowledged. Claim Objections Claim 21 is objected to because of the following informalities: in line 1, “Electronic” should not be capitalized. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claims 12-13, the phrase "for example" renders the claim indefinite because it is unclear whether the limitation(s) following the phrase are part of the claimed invention. See MPEP § 2173.05(d). For purposes of examination, it is assumed that whatever is after the phrase is not part of the claimed subject matter. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 8-12, 14-15, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al., US 2014/0332887. Zhang et al. shows the invention as claimed including an electronic device, comprising: A silicon layer (see layer including body region 203) having a first surface and a second surface, An insulating layer 202 in contact with the first surface of the silicon layer, At least one transistor comprising source 241, drain 242, and body regions 203 arranged in the silicon layer, and a gate region 245 topping the body region and comprising a gate portion laterally extending beyond the source and drain regions (see fig. 5), the body region being continued by a body contact region 240 not covered with the gate region, and a region of extension of the body region being located under the gate portion (see, for example, fig. 12 and paragraphs 0016-0031); The device further comprising, under the gate portion, a partial insulating trench 210 in the silicon layer extending from the second face of said silicon layer down to a depth smaller than the thickness of said silicon layer (see fig. 12). With respect to dependent claim 2, note that the body contact region 240 is laterally positioned next to the gate portion 245. Regarding dependent claim 3, note that the body region comprises a channel region between the source region and the drain region; and the gate region comprises a first portion topping the channel region, the gate portion being a second portion of the gate region continuing said first portion laterally above said channel region. With respect to dependent claim 8, note that the body contact region 240, the source region 241, and the drain region 242 are flush with the second surface of the silicon layer (see figs. 5 and 12 and their descriptions). Concerning dependent claim 9, note that the body contact region is separate from the partial insulating trench 240. In other words, the body contact region is not part of the partial insulating trench. Regarding dependent claim 10, note the presence of a first peripheral insulating trench 230 (right hand side in fig. 12), the body contact region 240 being laterally positioned between said first peripheral insulating trench and the partial insulating trench. As to dependent claim 11, note the presence of a second peripheral insulating trench 230 (left hand side of fig. 5), the source and drain regions being laterally positioned between said second peripheral insulating trench and the partial insulating trench. Concerning dependent claim 12, note that Zhang et al. discloses wherein the at least one transistor is a transistor on a structure of silicon-on-insulator type comprising the silicon layer 203, the insulating layer 202, and a substrate 201 topped with said insulating layer. With respect to dependent claim 14, note that Zhang et al. comprises a gate insulator layer between the gate region and the silicon layer (see fig. 12). Concerning dependent claim 15, note that Zhang et al. discloses wherein the gate insulator has under a portion of the gate portion, a thickness 210 greater than the thickness of the rest of the gate insulator (see fig. 4). As to independent claim 18, note that Zhang et al. includes a device, comprising: A substrate (201,202); A silicon layer 203 on the substrate; A body contact region 240 in the silicon layer, the body contact region having a first surface spaced from the substrate by a first distance; A trench 210 in the silicon layer adjacent to the body contact region; A gate region 245 on the silicon layer and on the trench, the gate region having a second surface spaced from the substrate by a second distance, the second distance being greater than the first distance. With respect to dependent claim 19, note that the gate region includes a sidewall that faces the body region (see fig. 12). Concerning independent claim 20, note that Zhang et al. discloses an electronic device, comprising: A silicon layer (see layer including body region 203) including a first surface; An insulating layer 202 in contact with the first surface of the silicon layer; A transistor, including: a source region 241 in the silicon layer; a drain region 242 in the silicon layer; a body region in the silicon layer and including an extension region 203 and a body contact region 240; and A gate region 245 including a gate portion laterally extending beyond the source and drain regions (see fig. 5), wherein the body contact region is not covered by the gate region, wherein the extension region of the body region is under the gate region (see, for example, fig. 12); and a trench 210 under the gate region in the silicon layer extending partially through the silicon layer (see paragraphs 0016-0031). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al., US 2014/0332887. Zhang et al. is applied as above but does not expressly disclose wherein the partial insulating trench has a width greater than or equal to the width of the gate portion and wherein the ratio of the depth of the insulating trench to the thickness of the silicon layer is in the range from approximately 0.2 to 0.8. Regarding the relative dimensions of the partial insulating trench, a prima facie case of obviousness exists because where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. Claim(s) 6-7 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al., US 2014/0332887 in view of Nakamura et al., U.S. Patent 12,453,122. Zhang et al. is applied as above but does not expressly disclose a first contact coupled to the body contact region and a second contact coupled to the gate region. Nakamura et al. discloses a semiconductor device which comprises both a body contact and a gate contract (see fig. 1 and its description). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the primary reference of Zhang et al. so as to comprise the claimed body and gate contacts because Nakamura et al. shows that such connections are part of conventional devices. Regarding the contact pad being a silicide, the examiner takes official notice that the use of silicides for contacts is well known in the art due to their high conductivity and relatively high melting point and would have been obvious to one of ordinary skill in the art at the time the invention was filed to implement in the claimed invention. Allowable Subject Matter Claim 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li et al., US 2011/0079851 discloses a body contact region that is formed outside the gate region (see, for example, fig. 20). Additionally, Unnikrishnan US 2003/0111693 discloses the formation of a body contact on a silicon-on-insulator substrate (see abstract). Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A BOOTH whose telephone number is (571)272-1668. The examiner can normally be reached Monday to Friday, 8:30 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A BOOTH/ Primary Examiner, Art Unit 2812 November 4, 2025
Read full office action

Prosecution Timeline

Mar 27, 2023
Application Filed
Nov 06, 2025
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.4%)
2y 4m
Median Time to Grant
Low
PTA Risk
Based on 1029 resolved cases by this examiner. Grant probability derived from career allow rate.

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