Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Second Non-Final
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/25/2026 and 04/10/2026 was considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 12-15, filed December 04, 2025, with respect to the rejection(s) of claims 1-10 and 12-20 under U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. A new ground(s) of rejection is necessitated by the amendment. The deficiencies of The deficiencies of Eldridge in view of Wie are now met by a combination of Eldridge in view of Wahio in view of Ebara. Applicant’s arguments with respect to claims 1-10 and 12-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge et al. US 6,483,328 B1 (hereinafter referred to as Eldridge) in view of Wahio et al. US 20110018564 A1 (hereinafter referred to as Wahio).
Regarding claim 1, Eldridge discloses a test method (fig. 3, col. 3, ln. 57-67) comprising: a panel level package (fig. 3, semiconductor wafer 310, col. 3, 57-59) formed with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26), the panel level package having a placement unit side (fig. 1-3, semiconductor wafer 208 side opposite has terminals 226 with raised contact elements, col. 3, ln. 14-24); bringing at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) electrically connected to at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55), of a test circuit (fig. 3, probe card 321, col. 3, 45-47) to into contact with at least one terminal (fig. 2-3, terminal 226, col. 3, 14-22) of at least one device of the plurality of devices (fig. 3, semiconductor devices 311, col. 3, 57-59), respectively the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) of the panel level package on a side opposite (see fig. 1-3) to a first surface (fig. 1-3, side closest to probe card); and testing, by the test circuit, the at least one device electrically connected to the test circuit (fig. 3, elm. 311, col. 3, ln. 57-58) via the at least one contact (fig. 3, elm. 301, col. 3, ln. 64-67).
Eldridge does not disclose a placement unit; on the placement unit side in the panel level package; wherein the bringing into contact includes positioning a contactor provided with the at least one contact and the panel level package by using at least one positioning member provided on the panel level package and at least one positioning members included in the contactor, the at least one positioning member of the panel level package and the at least one positioning member of the contactor correspond to each other, the at least one positioning member of the panel level package having a shape that is complementary to the at least one positioning member of the contactor, and then bringing the at least one contact into contact with the at least one terminal, respectively.
Wahio discloses a placement unit (fig. 1-5, tray holder 19, par. [0051]); on the placement unit side (fig. 1-5, side closest to the tray holder 19) in the panel level package (fig. 7, wafer 2, par. [0078]); wherein the bringing into contact includes positioning a contactor (fig. 7, probe card 40, par. [0078]) provided with the at least one contact (fig. 7, positioning pins 41, par. [0078]) and the panel level package (fig. 7, wafer 2, par. [0078]) by using at least one positioning member (fig. 7, marks of the wafer 2, alignment portions 13, par. [0078]) provided on the panel level package (fig. 7, wafer 2, par. [0078]) and at least one positioning members included in the contactor, the at least one positioning member of the panel level package and the at least one positioning member of the contactor correspond to each other (fig. 7-8, par. [0078]); and then bringing the at least one contact (fig. 20, probe needle 40A, par. [0079]) into contact with the at least one terminal (fig. 20, electrode of the wafer 2, par. [0079]), respectively.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide inspection method that can position an inspection target to be placed on a tray with respect to the tray and inspect a plurality of the inspection targets at the same time while transporting them with the tray, as taught in Wahio in modifying the apparatus of Eldridge. The motivation would be to accurately position a probe card with respect to the inspection target at inspection.(see Wahio: [par.[0003]).
Wahio discloses fitting three positioning pins on the contact unit side, in the V-grooves displaced by 120 degrees each, the tray is positioned at three positions displaced by degrees each. As a result, the tray is positioned with respect to the contact unit, and the wafer placed at the set position on the tray is positioned with respect to the probe card of the contact unit. Changing the location of in the V-grooves displaced by 120 degrees from the location shown by Wahio to a location on where the in the V-grooves are positioned on the wafer and repositioning the positioning pins to be complementary the position of the grooves, absent any criticality, is only considered to be an obvious modification of the Wahio device, that a person ordinary skill in the art before the effective filing date of the claimed invention would be able to provide using routine experimentation since the courts have held that there is no invention in shifting the position if the operation of the device would not be thereby modified. See In re Japikse, 86 USPQ 70 (CCPA 1950) and MPEP 2144.04 VI.
Regarding claim 9, Eldridge and Wahio discloses the test method according to claim 1, further comprising executing, before the placing, a functional test in order to individually confirm operations of a plurality of semiconductor chips and forming the plurality of devices by using a plurality of semiconductor chips determined to be non-defective products as a result of this (fig. 3, col. 3, ln. 23-24).
Regarding claim 12, Eldridge and Wahio discloses a manufacturing method comprising: Wahio discloses testing, in a panel level package formed with a plurality of unsingulated devices, the plurality of devices by the test method (abs.) according to claim 1; and cutting out and singulating (abs.) the plurality of devices (fig. 3, chip package structure 2, abs., Specific imp. ex, 3rd par) from the panel level package (fig. 3, multi-chip package structure, abs., Specific imp. ex, 3rd par).
The references are combined for the same reason already applied in the rejection of claim 1.
Regarding claim 13, Eldridge and Wahio discloses the manufacturing method according to claim 12, further Wahio discloses comprising selecting a plurality of singulated devices by using a result of a test by the test circuit (Specific imp. ex, 9th par.).
Claim(s) 4, 10, 14 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio in view of Ebara US 2008/0210935 A1.
Regarding claim 4, Eldridge discloses a test method (fig. 3, col. 3, ln. 57-67) comprising: a panel level package (fig. 3, semiconductor wafer 310, col. 3, 57-59) with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26), (fig. 3, elm. 311, col. 3, ln. 57-58), the panel level package having a placement unit side (fig. 1-3, semiconductor wafer 208 side opposite has terminals 226 with raised contact elements, col. 3, ln. 14-24); bringing at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) electrically connected to at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55), of a test circuit (fig. 3, probe card 321, col. 3, 45-47) into contact with at least one terminal (fig. 2-3, terminal 226, col. 3, 14-22) of at least one device of the plurality of devices (fig. 3, semiconductor devices 311, col. 3, 57-59), respectively, the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) panel level package on a side opposite (see fig. 1-3) to a first surface (fig. 1-3, side closest to probe card) of the panel level package,
Eldridge does not disclose a placement unit, on a placement unit, a panel level package formed with a plurality of unsingulated devices, the first surface of the panel level package being on the placement unit side of the panel level package; and testing, by the test circuit the at least one device electrically connected via the at least one contact wherein each of the plurality of devices has a plurality of terminals the plurality of terminals of each of the plurality of devices includes at least one terminal selected from a group consisting of a test terminal and a pin, which are exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package, and the plurality of terminals of each of the plurality of devices further includes one or more balls on each of the plurality of devices on the second surface of the panel level package, the at least one terminal of the at least one device is one of the plurality of terminals of the at least one device, the plurality of terminals of the at least one device includes at least one terminal selected from a group consisting of the test terminal and the pin, and the plurality of terminals of each of the at least one device further includes one or more balls on the at least one device on the second surface of the panel level package, and the testing includes testing, by the test circuit, the at least one device in a state where the at least one contact is electrically connected to the test terminal or pin of the at least one device and then testing the at least one device in a state where the at least one contact is electrically connected to at least one of the one or more balls of the at least one device.
Wahio discloses a placement unit (fig. 1-5, tray holder 19, par. [0051]); the first surface of the panel level package (fig. 7, chip formed on the wafer 2, par. [0081]) being on the placement unit side of the panel level package (see fig. 2-6);
The references are combined for the same reason already applied in the rejection of claim 1.
Ebara discloses testing, by the test circuit (fig. 3, probe wire 21, par. [0018]) the at least one device electrically connected via the at least one contact (fig. 3, col. 3, ln. 64-67), wherein each of the plurality of devices (fig. 7-8, chip areas 3, par. [0056]) has a plurality of terminals (fig. 8, bonding pad 9, probing pad 11, par. [0057]) the plurality of terminals of each of the plurality of devices includes at least one terminal selected from a group consisting of a test terminal (fig. 8, probing pad 11, par. [0057]) and a pin (fig. 8, bonding pad 9, par. [0057]), which are exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package (fig. 1-17, par.[0051]-[0077]), and the plurality of terminals (fig. 8, bonding pad 9, probing pad 11, par. [0057]) of each of the plurality of devices further on each of the plurality of devices on the second surface of the panel level package (fig. 1-17, elm. 17-5, par. [0059]-[0065]), the at least one terminal of the at least one device is one of the plurality of terminals of the at least one device (fig. 1-17, metal wiring layer 17-5, metal wiring layer, bonding pad 9 and the probing pad 11 are electrically connected to each other by disposing the metal wiring layer 17-2b so as to straddle the chip area 3 and the scribe line area 5, par. [0059]-[0065], [0083]-[0083]), the plurality of terminals of the at least one device includes at least one terminal selected from a group consisting of the test terminal and the pin (bonding pad 9, probing pad 11), and the plurality of terminals of each of the at least on the at least one device on the second surface of the panel level package (fig. 3, semiconductor wafer 300 is provided with a plurality of chip areas 3, par. [0056]-[0057]), and the testing includes testing, by the test circuit (fig. 3, elm. 21, par. [0073]), the at least one device in a state where the at least one contact is electrically connected to the test terminal or pin (fig. 8, bonding pad 9, probing pad 11, par. [0057]) of the at least one device and then testing the at least one device in a state where the at least one contact is electrically connected to at least of the at least one device (wafer test, the probing pad 11 and the probe wire 21 are kept in contact with each other, par. [0068]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal., as taught in Ebara in modifying the apparatus of Eldridge and Wahio. The motivation would be the wiring for pad connection is cut when the wafer is cut along the scribe line, the bonding and probing pads are isolated reliably. Short circuiting of the bonding pad and the internal wiring due to damage of the probing pad is avoided. (see Ebara: par. [0023]).
Eldridge, Wahio and Ebara discloses the claimed invention except for plurality of devices further includes one or more balls. These limitations with regard to the choice of electrical contact used on semiconductor package devices, absent any criticality, is only considered to be an obvious modification or choice the type of electrical contact, since it appears to the Examiner that a the choice of electrical contact used to electrically connect semiconductor package devices to other electrical circuits or devices that a person having ordinary skill in the art will find obvious to provide. In this case to provide high pin density, superior heat dissipation and improved electrical performance.
Regarding claim 10, Eldridge discloses a test method (fig. 3, col. 3, ln. 57-67) comprising: placing, a panel level package (fig. 3, semiconductor wafer 310, col. 3, 57-59) formed with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26), (fig. 3, elm. 311, col. 3, ln. 57-58), the panel level package having a placement unit side (fig. 1-3, semiconductor wafer 208 side opposite has terminals 226 with raised contact elements, col. 3, ln. 14-24); bringing at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) electrically connected to at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55) of a test circuit (fig. 3, probe card 321, col. 3, 45-47) into contact with at least one terminal (fig. 2-3, terminal 226, col. 3, 14-22) of at least one device of the plurality of devices (fig. 3, semiconductor devices 311, col. 3, 57-59), respectively, the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) of the panel level package (fig. 3, elm. 310) on a side opposite to a first surface (fig. 1-3, side closest to probe card) of the panel level package and testing, by the test circuit (fig. 3, probe card 321, col. 3, 45-47), the at least one device electrically connected via the at least one contact (fig. 3, col. 3, ln. 64-67).
Eldridge does not disclose the first surface of the panel level package being on the placement unit side of the panel level package; wherein in the panel level package, the plurality of devices are arranged in a matrix, further comprising: bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead- out wirings to an internal circuit of each device in each row of the plurality of devices, respectively; and testing, by the test circuit, the at least one device electrically connected via the plurality of contacts.
Wahio discloses the panel level package (fig. 7, chip formed on the wafer 2, par. [0081]) being on the placement unit side (fig. 1-5, side closest to the tray holder 19) of the panel level package.
The references are combined for the same reason already applied in the rejection of claim 1.
Ebara discloses the plurality of devices (fig. 7-8, chip areas 3, par. [0056]), are arranged in a matrix (fig. 7, semiconductor wafer 300 is provided with a plurality of chip areas 3 that are arranged in a matrix form, par. [0056])(clm. 1), further comprising: bringing a plurality of contacts electrically connected to a plurality of terminals of a test circuit into contact with a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead- out wirings to an internal circuit of each device in each row of the plurality of devices (fig. 1-17, semiconductor wafer 300 is diced along the scribe line area 5, elm. 17-5, metal wiring layer, bonding pad 9 and the probing pad 11 are electrically connected to each other by disposing the metal wiring layer 17-2b so as to straddle the chip area 3 and the scribe line area 5, par. [0059]-[0065], [0083]-[0083]), respectively; and testing, by the test circuit, the at least one device electrically connected via the plurality of contacts (fig. 6, wafer test is performed while contacting the probe wire 21 to the probing pad 11, the semiconductor wafer 300 is diced along the scribe line area 5. At this time, an end of the metal wiring layer 17-5b opposite to the probing pad 11, the metal wiring layer 17-4b, the metal wiring layer 17-3b, and an end of the metal wiring layer 17-2b opposite to the metal wiring layer 17-2a, the bonding pad 9 and the probing pad 11 are electrically separated from each other, par. [0073]).
The references are combined for the same reason already applied in the rejection of claim 4.
Regarding claim 14, Eldridge discloses a test apparatus (fig. 3, col. 3, ln. 57-67): a panel level package (fig. 3, semiconductor wafer 310, col. 3, ln. 57-59) formed with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26); a contactor (fig. 3, elm. 321, col. 3, pg. 47-48) configured to bring at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) into contact with at least one terminal (fig. 3, terminal 336, col. 3, ln. 44-45) of at least one device of the plurality of devices (311), respectively, the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) of the panel level package on a side opposite (see fig. 1-3) to a first surface (fig. 1-3, side closest to probe card) of the panel level package, the first surface of the panel level package being on the placement unit side of the panel level package; a test circuit (fig. 3, probe card 321, col. 3, ln. 45-47) which has at least one terminal (fig. 3, microspring contact 301, col. 3, ln. 60-63) electrically connected to the at least one contact and is configured to test the at least one device electrically connected via the at least one contact (fig. 3, col. 3, ln. 64-67).
Eldridge does not disclose the panel level package having a placement unit side, a placement unit; the contactor including at least one positioning member, wherein at least one positioning member is provided on the panel level package, which corresponds to the positioning member of the contactor, the at least one positioning member of the panel level package having a shape that is complementary to the at least one positioning member of the contactor, and the at least one contact is brought into contact with the at least one terminal by using the at least one positioning member of the panel level package and the at least one positioning member of the contactor to position the contactor and the panel level package relative to each other.
Wahio discloses a placement unit (fig. 1-5, tray holder 19, par. [0051]); the panel level package (fig. 7, wafer 2, par. [0078]) having a placement unit side (see fig. 1-5), the contactor (fig. 7, probe card 40, par. [0078]) including at least one positioning member (fig. 7, positioning pin 41, par. [0063]), wherein at least one positioning member (fig. 7, marks of the wafer 2, alignment portions 13, par. [0078]), is provided on the panel level package (fig. 7, wafer 2, par. [0078]), which corresponds to the positioning member of the contactor, and the at least one contact (fig. 20, probe needle 40A, par. [0079]) is brought into contact with the at least one terminal (fig. 20, electrode of the wafer 2, par. [0079]), by using the at least one positioning member of the panel level package (marks of the wafer 2) and the at least one positioning member (fig. 7, positioning pin 41, par. [0063]), of the contactor to position the contactor and the panel level package relative to each other (see fig. 20-22).
The references are combined for the same reason already applied in the rejection of claim 1.
Wahio discloses fitting three positioning pins on the contact unit side, in the V-grooves displaced by 120 degrees each, the tray is positioned at three positions displaced by degrees each. As a result, the tray is positioned with respect to the contact unit, and the wafer placed at the set position on the tray is positioned with respect to the probe card of the contact unit. Changing the location of in the V-grooves displaced by 120 degrees from the location shown by Wahio to a location on where the in the V-grooves are positioned on the wafer and repositioning the positioning pins to be complementary the position of the grooves, absent any criticality, is only considered to be an obvious modification of the Wahio device, that a person ordinary skill in the art before the effective filing date of the claimed invention would be able to provide using routine experimentation since the courts have held that there is no invention in shifting the position if the operation of the device would not be thereby modified. See In re Japikse, 86 USPQ 70 (CCPA 1950) and MPEP 2144.04 VI.
Regarding claim 20, Eldridge discloses a test apparatus (fig. 3, col. 3, ln. 57-67) comprising: a placing means on which a panel level package (fig. 3, semiconductor wafer 310, col. 3, 57-59) formed with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26), is placed, the panel level package having a placement unit side (fig. 1-3, semiconductor wafer 208 side opposite has terminals 226 with raised contact elements, col. 3, ln. 14-24); a contact means (fig. 3, probe card 321, col. 3, 45-47) configured to bring at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) into contact with at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55) of at least one device of the plurality of devices (fig. 3, semiconductor devices 311, col. 3, 57-59), respectively, the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) of the panel level package on a side opposite to a first surface of the panel level package; and a test means (fig. 3, semiconductor devices 311, col. 3, 57-59), which has at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55) electrically connected to the at least one contact (fig. 3, elm. 301, col. 3, ln. 64-67).
Eldridge does not disclose the first surface of the panel level package being on the placing means side of the panel level package; configured to test the at least one device electrically connected via the at least one contact, wherein in the panel level package, the plurality of devices are arranged in a matrix, the panel level package further comprises a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices, respectively, the contact means comprises a plurality of contacts electrically connected to a plurality of terminals of a test circuit, the contact means is configured to bring the plurality of contacts into contact with the plurality of contact terminals on one side in the panel level package in order to electrically connect the at least one device to the test circuit via the plurality of contacts and allow testing, by the test circuit, of the at least one device.
Wahio discloses the first surface of the panel level package (fig. 7, wafer 2, par. [0078]) being on the placing means side (fig. 1-5, side closest to the tray holder 19, par. [0051]) of the panel level package;
The references are combined for the same reason already applied in the rejection of claim 1.
Ebara discloses configured to test (fig. 3, probe wire 21, par. [0018]) the at least one device electrically (fig. 7-8, chip areas 3, par. [0056]) connected via the at least one contact (fig. 3, probing pad 11 col. 3, ln. 64-67), wherein in the panel level package (fig. 1-17, semiconductor wafer 300, par. [0008]-[0010], [0052]-[0059]), the plurality of devices are arranged in a matrix (fig. 7, semiconductor wafer 300 is provided with a plurality of chip areas 3 that are arranged in a matrix form, par. [0056])(clm. 1), the panel level package further comprises a plurality of contact terminals provided on one side in the panel level package in a row direction of the matrix and connected via a plurality of lead-out wirings to an internal circuit of each device in each row of the plurality of devices (fig. 1-17, semiconductor wafer 300 is diced along the scribe line area 5, elm. 17-5, metal wiring layer, bonding pad 9 and the probing pad 11 are electrically connected to each other by disposing the metal wiring layer 17-2b so as to straddle the chip area 3 and the scribe line area 5, par. [0059]-[0065], [0083]-[0083]), respectively, the contact means comprises a plurality of contacts electrically connected to a plurality of terminals (fig. 1-17, 17-5, metal wiring layer, bonding pad 9 and the probing pad 11 are electrically connected to each other by disposing the metal wiring layer 17-2b so as to straddle the chip area 3 and the scribe line area 5, par. [0059]-[0065], [0083]-[0083]), of a test circuit (fig. 3, probe wire 21, par. [0018]) the, the contact means is configured to bring the plurality of contacts into contact with the plurality of contact terminals on one side in the panel level package in order to electrically connect the at least one device to the test circuit via the plurality of contacts and allow testing, by the test circuit, of the at least one device (fig. 6, wafer test is performed while contacting the probe wire 21 to the probing pad 11, the semiconductor wafer 300 is diced along the scribe line area 5. At this time, an end of the metal wiring layer 17-5b opposite to the probing pad 11, the metal wiring layer 17-4b, the metal wiring layer 17-3b, and an end of the metal wiring layer 17-2b opposite to the metal wiring layer 17-2a, the bonding pad 9 and the probing pad 11 are electrically separated from each other, par. [0073]).
The references are combined for the same reason already applied in the rejection of claim 4.
Regarding claim 21, Eldridge discloses a test apparatus (fig. 3, col. 3, ln. 57-67) comprising: a panel level package (fig. 3, semiconductor wafer 310, col. 3, 57-59) with a plurality of unsingulated devices (fig. 2, semiconductor devices to test devices while still unsingulated from the wafer, col. 1, ln. 23-26), (fig. 3, elm. 311, col. 3, ln. 57-58), is placed, the panel level package having a placement unit side (fig. 1-3, semiconductor wafer 208 side opposite has terminals 226 with raised contact elements, col. 3, ln. 14-24); at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) into contact with at least one terminal (fig. 2-3, elm. 332, col. 3, ln. 47-55) of at least one device of the plurality of devices (fig. 3, semiconductor devices 311, col. 3, 57-59), respectively, the terminal being exposed on a second surface (fig. 1-3, semiconductor wafer 208 side which has terminals 226 with raised contact elements, col. 3, ln. 14-24) of the panel level package on a side opposite to a first surface (fig. 1-3, side closest to probe card) of the panel level package; and a test means (fig. 3, probe card 321, col. 3, 45-47) which has at least one terminal (fig. 2-3, terminal 226, col. 3, 14-22) electrically connected to the at least one contact (fig. 3, microspring contact 301, col. 3, 60-63) and is configured to test the at least one device electrically connected via the at least one contact, wherein each of the plurality of devices (fig. 3, elm. 311, col. 3, ln. 57-58), has a plurality of terminals (see fig. 3),.
Eldridge does not disclose a placing means on which a panel level package formed with a plurality of unsingulated devices is placed; the first surface of the panel level package being on the placing means side of the panel level package; a contact means configured to bring at least one contact into contact with at least one terminal; the plurality of terminals of each of the plurality of devices includes at least one terminal selected from a group consisting of a test terminal and a pin, which are exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package, and the plurality of terminals of each of the plurality of devices further includes one or more balls on each of the plurality of devices on the second surface of the panel level package, the at least one terminal of the at least one device is one of the plurality of terminals of the at least one device, the plurality of terminals of the at least one device includes at least one terminal selected from a group consisting of the test terminal and the pin, and the plurality of terminals of each of the at least one device further includes one or more balls on the at least one device on the second surface of the panel level package, and the test means is configured such that the test means tests the at least one device in a state where the at least one contact is electrically connected to the test terminal or pin of the at least one device and then the test means tests the at least one device in a state where the at least one contact is electrically connected to at least one of the one or more balls of the at least one device
Wahio discloses a placing means (fig. 1-5, tray holder 19, par. [0051]) on which a panel level package (fig. 7, chip formed on the wafer 2, par. [0081]) formed with a plurality of unsingulated devices (fig. 5, 20, wafer 2 (a specific chip formed on the wafer 2 or its electrode pad, for example) par.[0081]) is placed; the first surface (see fig. 2-5) of the panel level package being on the placing means side (fig. 1-5, side closest to the tray holder 19) of the panel level package.
The references are combined for the same reason already applied in the rejection of claim 1.
Ebara discloses the plurality of terminals of each of the plurality of devices (fig. 7-8, chip areas 3, par. [0056]) includes at least one terminal selected from a group consisting of a test terminal and a pin (fig. 8, probing pad 11, par. [0057]) and a pin (fig. 8, bonding pad 9, par. [0057]), which are exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package (fig. 3, semiconductor wafer 300 is provided with a plurality of chip areas 3, par. [0056]-[0057]),and the plurality of terminals of each of the plurality of devices further on each of the plurality of devices on the second surface of the panel level package, the at least one terminal of the at least one device is one of the plurality of terminals of the at least one device, the plurality of terminals (fig. 1-17, metal wiring layer 17-5, metal wiring layer, bonding pad 9 and the probing pad 11 are electrically connected to each other by disposing the metal wiring layer 17-2b so as to straddle the chip area 3 and the scribe line area 5, par. [0059]-[0065], [0083]-[0083]) of the at least one device includes at least one terminal selected from a group consisting of the test terminal and the pin, and the plurality of terminals of each of the at least one device on the at least one device on the second surface of the panel level package (fig. 3, semiconductor wafer 300 is provided with a plurality of chip areas 3, par. [0056]-[0057]), and the test means (fig. 3, probe wire 21, par. [0018]) is configured such that the test means tests the at least one device in a state where the at least one contact is electrically connected to the test terminal or pin (fig. 8, bonding pad 9, probing pad 11, par. [0057]) of the at least one device and then the test means tests the at least one device in a state where the at least one contact is electrically connected to the at least one device (wafer test, the probing pad 11 and the probe wire 21 are kept in contact with each other, par. [0068]); a contact means (fig. 1-5, alignment unit 4, par. [0091]-[0095]) configured to bring at least one contact into contact with at least one terminal;
The references are combined for the same reason already applied in the rejection of claim 4.
Eldridge, Wahio and Ebara discloses the claimed invention except for plurality of devices further includes one or more balls. These limitations with regard to the choice of electrical contact used on semiconductor package devices, absent any criticality, is only considered to be an obvious modification or choice the type of electrical contact, since it appears to the Examiner that a the choice of electrical contact used to electrically connect semiconductor package devices to other electrical circuits or devices that a person having ordinary skill in the art will find obvious to provide. In this case to provide high pin density, superior heat dissipation and improved electrical performance.
Claim(s) 2, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio as applied to claim 1 above respectively, and further in view of Chou et al. US 2020/0051902 A1 (hereinafter referred to as Chou)
Regarding claim 2, Eldridge and Wahio discloses the test method according to claim 1, Eldridge and Wahio do not disclose wherein the bringing into contact includes bringing the at least one contact into contact with the at least one terminal of the at least one device mounted with no ball
on the second surface of the panel level package, respectively.
Chou discloses wherein the bringing into contact includes bringing the at least one contact into contact with the at least one terminal (fig. 6-7, elm. 210, par. [0026]-[0027]) of the at least one device mounted (fig. 6-7, electronic devices 2301, 2302, par. [0026]-[0027]) with no ball on the second surface of the panel level package, respectively (see fig. 6, package structures 100, par. [0026]-[0027]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a manufactured package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface ,the electrical property and function can be tested in various phases of the fabrication processes to realize the qualities of the redistribution layer, the connection of the electronic devices with the redistribution layer, and the package structure, as taught in Chou in modifying the apparatus of Eldridge and Wahio. The motivation would be the manufactured package structure is prevented from having low product yield or performance due to the defects of the redistribution layer, and the cost waste of materials of following processes are prevented. The portion of the redistribution layer with worse performance or defect can be selectively repaired or excluded. The wasting resources on the portion of the package structure with defect is avoided. (see Chou, par. [0005]-[0008]).
Regarding claim 6, Eldridge and Wahio discloses the test method according to claim 1, Eldridge and Wahio do not disclose wherein the testing includes executing a functional test in order to individually confirm an operation of the at least one device.
Chou discloses wherein the testing includes executing a functional test in order to individually confirm an operation of the at least one device (fig. 6-7, electronic devices 2301, 2302, par. [0026]-[0027]).
The references are combined for the same reason already applied in the rejection of claim 2.
Claim(s) 15, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio in view of as Ebara applied to claim 14 above respectively, and further in view of Chou et al. US 2020/0051902 A1 (hereinafter referred to as Chou).
Regarding claim 15, Eldridge, Wahio and Ebara discloses the test apparatus according to claim 14, Eldridge, Wahio and Ebara do not disclose wherein the contactor is configured to bring the at least one contact into contact with the at least one terminal of the at least one device mounted with no ball on the second surface of the panel level package, respectively.
Chou discloses the contactor is configured to bring the at least one contact into contact with the at least one terminal (fig. 6-7, elm. 210, par. [0026]-[0027]) of the at least one device (fig. 6-7, electronic devices 2301, 2302, par. [0026]-[0027]) mounted with no ball on the second surface of the panel level package, respectively (see fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a manufactured package structure includes a redistribution layer having a first surface, a second surface disposed opposite to the first surface ,the electrical property and function can be tested in various phases of the fabrication processes to realize the qualities of the redistribution layer, the connection of the electronic devices with the redistribution layer, and the package structure, as taught in Chou in modifying the apparatus of Eldridge, Wahio and Ebara. The motivation would be the manufactured package structure is prevented from having low product yield or performance due to the defects of the redistribution layer, and the cost waste of materials of following processes are prevented. The portion of the redistribution layer with worse performance or defect can be selectively repaired or excluded. The wasting resources on the portion of the package structure with defect is avoided. (see Chou, par. [0005]-[0008]).
Regarding claim 17, Eldridge, Wahio and Ebara discloses the test apparatus according to claim 14, Eldridge, Wahio and Ebara do not disclose wherein the at least one terminal of the at least one device includes at least any one of a test terminal or pin exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package or balls on the plurality of devices on the second surface of the panel level package.
Chou discloses the at least one terminal of the at least one device (fig. 11, probe 230, par. [0032]) includes at least any one of a test terminal or pin (fig. 11, probe 312, par. [0030]) exposed from a region adjacent to each of the plurality of devices on the second surface of the panel level package or balls on the plurality of devices (fig. 11, probe 230, par. [0032]) on the second surface of the panel level package (fig. 11, package structure units UT, par. [0032]).
The references are combined for the same reason already applied in the rejection of claim 15.
Regarding claim 19, Eldridge, Wahio and Ebara discloses the test apparatus according to claim 14, Eldridge, Wahio and Ebara do not disclose wherein the test circuit is configured to execute a functional test in order to individually confirm an operation of the at least one device.
Chou discloses wherein the test circuit is configured to execute a functional test in order to individually confirm an operation of the at least one device (fig. 6-7, electronic devices 2301, 2302, par. [0026]-[0027]).
The references are combined for the same reason already applied in the rejection of claim 15.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio in view of Chou as applied to claim 6 above, and further in view of Komoto US 2012/0214261.
Regarding claim 7, Eldridge, Wahio and Chou discloses the test method according to claim 6, Eldridge, Wahio and Chou do not disclose further comprising executing, before the testing, temperature control to bring a temperature of the at least one device close to a target temperature.
Komoto discloses further comprising executing, before the testing, temperature control to b Komoto comprising executing, before the testing, a temperature of the at least one device close to a target temperature (fig. 14, par. [0077]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a temperature control section on a test board, as taught in Komoto in modifying the apparatus of Eldridge, Wahio and Chou. The motivation would be to control the device within the test package to be a prescribed temperature. (see Komoto: par. [0079]).
Regarding claim 8, Eldridge, Wahio and Chou discloses the test method according to claim 7, Eldridge, Wahio and Chou do not disclose wherein the executing the temperature control includes bringing, by a temperature adjustment unit provided in the placement unit, the first surface of the panel level package uniformly close to the target temperature.
Komoto discloses wherein the executing the temperature control includes bringing, by a temperature adjustment unit provided (fig. 14, elm. 74, par. [0077]) in the placement unit (fig. 14, test board 72, par. [0077]), the first surface of the panel level package uniformly close to the target temperature (par. [0079]).
The references are combined for the same reason already applied in the rejection of claim 6.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio in view of Chou as applied to claim 2 above, and further in view of Huang et al. US 2023/0045422 A1 (hereinafter referred to as Huang).
Regarding claim 3, Eldridge, Wahio and Chou discloses the test method according to claim 2, Eldridge, Wahio and Chou do not disclose wherein in the at least one device, at least one ball pad for mounting a ball and at least one sacrificial pad on which no ball is mounted are formed on the second surface of the panel level package, and the at least one terminal of the at least one device includes the at least one sacrificial pad and does not include the at least one ball pad.
Huang discloses wherein in the at least one device (fig. 12, semiconductor package, par. [0055]), at least one ball pad (fig. 12, aluminum pads 50, par. [0055]) for mounting a ball (fig. 12, conductive connectors 124, par. [0055]) and at least one sacrificial pad (fig. 12, sacrificial pad 52, par. [0055]) on which no ball is mounted are formed on the second surface of the panel level package (fig. 12, semiconductor package, par. [0055]), and the at least one terminal of the at least one device includes the at least one sacrificial pad and does not include the at least one ball pad (see fig. 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a method including attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, as taught in Huang in modifying the apparatus of Eldridge, Wahio and Chou. The motivation would be improved performance of the integrated circuits by minimizing or preventing undesired short circuits and parasitic capacitance (see Huang: par. [0058]).
Claim(s) 5, 16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eldridge in view of Wahio in view of Ebara as applied to claim 4, 15 and 17 above, and further in view of Huang et al. US 2023/0045422 A1 (hereinafter referred to as Huang).
Regarding claim 5, Eldridge, Wahio and Ebara discloses the test method according to claim 4, Eldridge, Wahio and Ebara do not disclose wherein in the at least one device, the one or more balls are formed more than the test terminals or pins.
Huang discloses wherein in the at least one device (fig. 2, first package component 40, par. [0017]), the one or more balls are formed more than the test terminals or pins (fig. 2, sacrificial pad 52, par. [0017]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a method including attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, as taught in Huang in modifying the apparatus of Eldridge, Wahio and Ebara. The motivation would be improved performance of the integrated circuits by minimizing or preventing undesired short circuits and parasitic capacitance (see Huang: par. [0058]).
Regarding claim 16, Eldridge, Wahio, Ebara and Chou discloses test apparatus according to according to claim 15, Eldridge, Wahio, Ebara and Chou do not disclose wherein in the at least one device, at least one ball pad for mounting a ball p and at least one sacrificial pad on which no ball is mounted are formed on the second surface of the panel level package, and the at least one terminal of the at least one device includes the at least one sacrificial pad and does not include the at least one ball pad.
Huang discloses wherein in the at least one device (fig. 12, semiconductor package, par. [0055]), at least one ball pad (fig. 12, aluminum pads 50, par. [0055]) for mounting a ball (fig. 12, conductive connectors 124, par. [0055]) and at least one sacrificial pad (fig. 12, sacrificial pad 52, par. [0055]) on which no ball is mounted are formed on the second surface of the panel level package (fig. 12, semiconductor package, par. [0055]), and the at least one terminal of the at least one device includes the at least one sacrificial pad and does not include the at least one ball pad (see fig. 12).
The references are combined for the same reason already applied in the rejection of claim 5.
Regarding claim 18, Eldridge, Wahio, Ebara and Chou discloses the test apparatus according to claim 17, Eldridge, Wahio, Ebara and Chou do not disclose wherein in the at least one device, the balls are formed more than the test terminals or pins, and the test circuit is configured to test the at least one device in a state where the at least one contact is electrically connected to the test terminal or pin of the at least one device and then test the at least one device in a state where the at least one contact is electrically connected to the ball of the at least one device.
Huang discloses wherein in the at least one device (fig. 2, first package component 40, par. [0017]), the balls are formed more than the test terminals or pins (fig. 2, sacrificial pad 52, par. [0017]), and the test circuit is configured to test the at least one device in a state where the at least one contact (fig. 2, probe 62 , par. [0017]) is electrically connected to the test terminal or pin of the at least one device and then test the at least one device (fig. 12, semiconductor package, par. [0055) in a state where the at least one contact (par. [0057]) is electrically connected to the ball (fig. 12, conductive connectors 124, par. [0055) of the at least one device.
The references are combined for the same reason already applied in the rejection of claim 5.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858
4/27/2026
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