DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/24/2025 has been entered.
Response to Arguments
Applicant’s response has been fully considered.
Applicant’s amendments to claims 4 and 5 overcome the previously raised objections.
Applicant’s amendments and the accompanying arguments with respect to a gate structure disposed over a first active area and a second active area in claim 1 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different interpretation of Choi et al. (US 9,646,711) and Siprak (WO 2017/217984).
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
In reference to claim 4, the claim requires “the at least one first gate via aligns with a center of the first active area and the at least one second gate via aligns with a center of the second active area.” Claim 4 depends on claim 1, and claim 1 establishes that at least one of the number of first gate vias and the number of second gate vias is more than 1. Plural gate vias being aligned with a center of the active area is not disclosed. Single gate vias are disclosed as aligned with the center of the active area, see paragraphs 55 and 58 of the specification, and via VG4 in Figure 4A, (aligned with the center of the active region in the y-direction) for example. However, as can be seen in Figure 4A, when there are multiple gate vias, such as vias VG3 and VG9, they are not aligned with the center of the active region.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends.
Claim 7 depends on claim 1 and requires “the conductive line is disposed above the first conductive segment,” which is previously claimed in the last line of claim 1. Therefore, claim 7 does not provide a further limitation to claim 1.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9,646,711) in view of Siprak (WO 2017/217984).
In reference to claim 1, Choi et al. (US 9,646,711), hereafter “Choi,” discloses a structure, with reference to Figure 8, comprising:
a gate structure 210 disposed over a first active area 120 and a second active area 130, respectively, col. 7 lines 30-39 ;
at least one first gate via 251, 253 and at least one second gate via 252 disposed on the gate structure, wherein a number of the at least one first gate via (2) and the at least one second gate via (1) are different; and
a conductive line 230, col. 13 line 60 to col. 14, line 5.
Choi does not disclose a first conductive segment and a second conductive segment connected to the at least one first gate via and the at least one second gate via, or
the conductive line is disposed above the first conductive segment.
Siprak (WO 2017/217984), hereafter ‘Siprak,” discloses a structure, with reference to Figure 6, comprising:
a first gate and a second gate 106;
at least one first gate via 305 disposed on the first gate and at least one second gate via 305 disposed on the second gate,
a first conductive segment 308 and a second conductive segment 308 connected to the at least one first gate via and the at least one second gate via, respectively; and
a conductive line 130 disposed above the first conductive segment, page 24, line 29 to page 25 line 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a first conductive segment and a second conductive segment to be connected to the at least one first gate via and the at least one second gate via, and
the conductive line to be disposed above the first conductive segment.
To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the conductive line in one metallization layer for a conductive line is a higher metallization layer.
In reference to claim 3, Choi discloses the at least one first gate via, 251, 253 is aligned along a width of the first active area 120 and the at least one second gate via 252 is aligned along a width of the second active area 130 (active area width being in the y-direction in Figure 8 of Choi).
In reference to claim 7, Choi in view of Siprak disclose the conductive line is disposed above the first conductive segment as addressed above in reference to claim 1.
Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 9,646,711) in view of Siprak (WO 2017/217984)as applied to claim 1 above and further in view of Kim et al. (US 2016/0300839).
In reference to claim 4, Choi in view of Siprak does not disclose the at least one first gate via aligns with a center of the first active area and the at least one second gate via aligns with a center of the second active area.
Kim et al. (US 2016/0300839), hereafter “Kim,” discloses an analogous device including teaching at least one first gate via, CB2a in Figure 2, aligns with a center of the first active area AR1 (in the x-direction) and the at least one second gate via CB2b aligns with a center of the second active area AR2 ( in the x-direction). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the at least one first gate via to align with a center of the first active area and the at least one second gate via to align with a center of the second active area.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the parallel connection over multiple vias as taught by Choi to the device layout of Kim.
In reference to claim 5, Choi does not disclose the gate structure is configured to be a terminal of a logic circuit.
Kim discloses an analogous device including teaching a gate structure, CL2 in Figure 2, is configured to be a terminal of a logic circuit (control signal B), Figures 1 and 4 and paragraphs 29-32 and 52. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the gate structure to be configured to be a terminal of a logic circuit.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the parallel connection over multiple vias as taught by Choi to the device layout of Kim.
In reference to claim 6, Choi discloses a second gate structure, 310 in Figure 15,
a third gate via 351 and a fourth gate via 353 disposed on the second gate structure, col. 17 line 55 to col. 18 line 4.
Choi does not disclose a third conductive segment and a fourth conductive segment coupled to the second gate structure wherein the second gate structure is configured to be a terminal of an other logic circuit coupled to the logic circuit.
Siprak discloses second gate structure 106L;
a third gate via 305 and a fourth gate via 305 disposed on the second gate structure,
a third conductive segment 308 and a fourth conductive segment 308 coupled to the second gate structure, page 24, line 29 to page 25 line 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a third conductive segment and a fourth conductive segment to be coupled to the second gate structure.
To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting the conductive line in one metallization layer for a conductive line is a higher metallization layer.
Siprak does not disclose the second gate structure is configured to be a terminal of an other logic circuit coupled to the logic circuit.
Kim teaches a second gate structure, CL1 in Figure 4, is configured to be a terminal of an other logic circuit coupled to the logic circuit (control signal A), Figures 1 and 4 and paragraphs 29-32 and 50.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the second gate structure to be configured to be a terminal of an other logic circuit coupled to the logic circuit.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the parallel connection over multiple vias as taught by Choi to the device layout of Kim.
Allowable Subject Matter
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
In reference to claims 8 and 17, the prior art of record to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding plural first gate vias and second gate vias wherein the first gate vias and the second gate vias comprise a different number of first gate vias and second gate vias on a single, shared, gate structure; in combination with the other recited limitations. Claims 9-16 depend on claim 8 and claims 18-20 depend on claim 17.
The closest prior art of record is Park et al. (US 2004/0169207) which discloses first and second transistors with different numbers of gate vias, however, with one transistors with a single gate via 11a and another transistor with multiple vias, 11b, 11c, see Figure 2.
The instant application differs from the prior art in that the instant application includes both gates having multiple gate vias over a single, shared, gate structure. This structure is not taught or rendered obvious by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897