DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I (original claims 1-10 and new claim 21) in the reply filed on 1.21.2026 is acknowledged. The traversal is on the ground(s) that Group I and Group III (claims 17-20 and new claim 22) are no longer distinct or independent since claim 17 was amended on 1.21.2026; the applicant further alleges new claims 23-26 should be examined together with claims 1-10 and 17-22. This is persuasive as claims 1-10 and 17-26 belong to the same invention (i.e., elected Group I).
Applicant’s election without traverse of Species A (Figs. 1-13) in the reply filed on 1.21.2026 is acknowledged. Applicant confirmed on 3.23.2026 that claims 8-9 are withdrawn and claims 1-7, 10 and 17-26 read on the elected species.
Claims 8-9 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1.21.2026 and the subsequent communication of 3.23.2026.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in IT on 4.8.2022. It is noted, however, that applicant has not filed a certified copy of the IT102022000007052 application as required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a vertical channel region extending from the second side of the wafer to the first side of the wafer” (claim 23; in Fig. 13, vertical-channel region 76 does not extend from 55A to 55B) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 17 is objected to because of the following informalities: “high” should read –higher--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 5-7, 10, and 17-26 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, “forming, in a work wafer of semiconductor material, a first doped region, the work wafer having a first side and a second side opposite to the first side along a direction, the first doped region being formed at the second side of the work wafer, the work wafer and the first doped region having a first conductivity type, the work wafer having a first doping level, the first doped region having a second doping level higher than the first doping level” causes the claim to fail to comply with the written description requirement because (a) original claims are subject to this requirement per MPEP 2163 and (b) the claim encompasses more embodiments than those disclosed.
In the instant case, the first doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion. This is significantly broader than the method disclosed in the specification at Fig. 4 and related text which only supports ion implantation.
Hence, the claim fails to comply with the written description requirement. Claims 2-4 address this deficiency since claim 2 recites introduction of dopant atoms and annealing thereof, but claims 5-7, 10 and 21 do not address this deficiency and are thereby rejected along with claim 1.
Regarding claim 7, “forming, in the work wafer and at the second side of the work wafer, a second doped region having a second conductivity type different from the first conductivity type, the second doped region extending in the work wafer from the second side of the work wafer and in contact with the first doped region” causes the claim to fail to comply with the written description requirement because (a) original claims are subject to this requirement per MPEP 2163 and (b) the claim encompasses more embodiments than those disclosed.
In the instant case, the second doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion. This is significantly broader than the method disclosed in the specification at Fig. 11 and related text which only supports ion implantation.
Hence, the claim fails to comply with the written description requirement. Claim 21 does not address this deficiency.
Regarding claim 17, “forming a first doped layer on a first side of a wafer, the first doped layer and the wafer having a first conductivity type, the first doped layer having a high doping level than the wafer; annealing the first doped layer and the wafer” causes the claim to fail to comply with the written description requirement because the claim encompasses more embodiments than those disclosed.
In the instant case, the first doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion followed by an anneal. This is significantly broader than the method disclosed in the specification at Fig. 4 and related text which only supports ion implantation followed by an anneal.
Hence, the claim fails to comply with the written description requirement. Claims 18-20 and 22 do not address this deficiency and are thereby rejected along with claim 17.
Regarding claim 22, “forming a second doped layer on the first side of the wafer, the second doped layer being spaced from the wafer by the first doped layer, the second doped layer having a second conductivity type; and forming a metallization layer on the second doped layer” causes the claim to fail to comply with the written description requirement because the claim encompasses more embodiments than those disclosed.
In the instant case, the second doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion. This is significantly broader than the method disclosed in the specification at Fig. 11 and related text which only supports ion implantation.
Hence, the claim fails to comply with the written description requirement.
Regarding claim 23, “forming, in a first side of a wafer having a first conductivity type, a first doped layer having the first conductivity type, the first doped layer having a higher doping level than the wafer” causes the claim to fail to comply with the written description requirement because the claim encompasses more embodiments than those disclosed.
In the instant case, the first doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion. This is significantly broader than the method disclosed in the specification at Fig. 4 and related text which only supports ion implantation followed by an anneal.
Furthermore, “a vertical channel region extending from the second side of the wafer to the first side of the wafer” is not supported by the specification/drawings as originally filed because in Fig. 13, for example, vertical-channel region 76 does not extend from side 55A to side 55B. Vertical-channel region 76 is located between sides 55A and 5B but does not extend from one to the other as claimed and it is new matter.
Hence, the claim fails to comply with the written description requirement. Claims 24-26 do not address these deficiencies and are thereby rejected along with claim 23.
Regarding claim 26, “forming a second doped layer on the first side of the wafer, the second doped layer being spaced from the wafer by the first doped layer, the second doped layer having a second conductivity type” causes the claim to fail to comply with the written description requirement because the claim encompasses more embodiments than those disclosed.
In the instant case, the second doped region as claimed can be formed by any method such as epitaxial growth or solid source diffusion. This is significantly broader than the method disclosed in the specification at Fig. 11 and related text which only supports ion implantation.
Hence, the claim fails to comply with the written description requirement.
Claims 23-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 23, “a vertical channel region extending from the second side of the wafer to the first side of the wafer” is not supported by the specification/drawings as originally filed because in Fig. 13, for example, vertical-channel region 76 does not extend from side 55A to side 55B. Vertical-channel region 76 is located between sides 55A and 5B but does not extend from one to the other as claimed which creates a conflict or an inconsistency with the specification and renders the claim indefinite per MPEP 2173.03. The claim is treated as presented or a supported by Fig. 13.
None of claims 24-26 address this deficiency.
Claim Rejections - 35 USC § 102 and 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 7, 17 and 20-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Janisch et al. (US 20180151367 A1).
Regarding claim 1, Janisch discloses a manufacturing process of a vertical-channel semiconductor device (IGBT, Fig. 2f), the manufacturing process comprising:
forming (Figs. 2a-2b), in a work wafer (101) of semiconductor material (“a low-doped n-type silicon wafer 101 having a front side 102 and a back side 103”), a first doped region (111/108, “thin phosphorous ion implantation layer 111”; phosphorous is an n-type dopant in silicon), the work wafer having a first side (102) and a second side (103) opposite to the first side along a (thickness) direction (Fig. 2a), the first doped region (111) being formed at the second side (103) of the work wafer, the work wafer and the first doped region having a first conductivity type (both are n-type; see above), the work wafer having a first doping level (“low-doped n-type silicon”), the first doped region having a second doping level (phosphorous implanted) higher than the first doping level (the addition of phosphorous which is an n-type dopant in silicon to an already low-doped n-type silicon to create element 111 implicitly discloses a higher doping level in 111 than 101); and
forming (Fig. 2e), in the work wafer and at the first side (102 now 102’ per Fig. 2d) of the work wafer, a device active region (104 and 101’), including a channel region (near gates 106) extending along the direction (thickness direction), the first doped region (now 108) and the device active region (104/101’) delimiting, in the work wafer, a drift region (bottom of 101’), forming of the first doped region (111/108) being performed before forming of the device active region (Figs. 2a-2c vs. 2e-2f).
Regarding claim 2, Janisch discloses the manufacturing process according to claim 1, wherein forming of the first doped region (111/108) includes: introducing dopant atoms into the work wafer (Fig. 2a, [0034]); and annealing (thermal oxidation) the work wafer so as to cause a diffusion of the dopant atoms in the work wafer (Fig. 2b, [0035]).
Regarding claim 5, Janisch discloses the manufacturing process according to claim 1, wherein the first doped region (111/108) includes dopant atoms selected from a group including phosphorus ([0034]), antimony, and arsenic.
Regarding claim 7, Janisch discloses the manufacturing process according to claim 1, further comprising: forming, in the work wafer and at the second side (103) of the work wafer, a second doped region (109, “p-type anode layer 109”) having a second conductivity type (p) different from the first conductivity type (n), the second doped region extending in the work wafer (101’) from the second side (103) of the work wafer and in contact with the first doped region (108. Fig. 2f).
Regarding claim 21, Janisch discloses the manufacturing process according to claim 7, further comprising: forming a metallization layer (110) on the second doped region (109, Fig. 2f).
Regarding claim 17, Janisch discloses a method, comprising:
forming a first doped layer (111/108) on a first side (103) of a wafer (101), the first doped layer (phosphorous; n-type) and the wafer (low-doped n-type) having a first conductivity type ([0034-0035]), the first doped layer having a high doping level than the wafer (the addition of phosphorous which is an n-type dopant in silicon to an already low-doped n-type silicon to create element 111/108 implicitly discloses a higher doping level in 111/108 than 101);
annealing the first doped layer and the wafer (thermal oxidation of [0035]); and
forming, subsequent to the annealing, a device functional layer (104/101’) on a second side (102’) of the wafer (Fig. 2f).
Regarding claim 20, Janisch discloses the method according to claim 17, further comprising: forming a vertical-channel semiconductor device (IGBT) in at least the device functional layer (Fig. 2f).
Regarding claim 22, Janisch discloses the method according to claim 17, further comprising:
forming a second doped layer (109) on the first side (103) of the wafer, the second doped layer being spaced from the wafer (101’) by the first doped layer (108), the second doped layer having a second conductivity type (p); and
forming a metallization layer (110) on the second doped layer (Fig. 2f).
Regarding claim 23, Janisch discloses a method, comprising:
forming, in a first side (103) of a wafer (101) having a first conductivity type (low doped n), a first doped layer (111/108) having the first conductivity type (additionally doped n), the first doped layer having a higher doping level than the wafer (inherent since additional n dopants are added to an n area. Figs. 2a-2c, [0034-0035]); and
forming, in a second side (102’) of the wafer, a device functional layer (104/101’, Fig. 2f); and
forming a vertical channel region (near gates 106) extending from (without reaching either; see 35 USC 112 rejection above) the second side (102’) of the wafer to the first side (103) of the wafer (Fig. 2f).
Regarding claim 24, Janisch discloses the method of claim 23, further comprising:
forming a diffused layer (109) in the first doped layer (Figs. 2d-2f); and forming a drift layer (bottom of 101’) in the wafer (101’, Fig. 2f).
Regarding claim 25, Janisch discloses the method of claim 24, wherein the device functional layer (104/101’) is (partly) formed in the drift layer (bottom of 101’, Fig. 2f).
Regarding claim 26, Janisch discloses the method according to claim 23, further comprising:
forming a second doped layer (109) on the first side (103) of the wafer, the second doped layer being spaced from the wafer (101’) by the first doped layer (108), the second doped layer having a second conductivity type (p); and
forming a metallization layer (110) on the second doped layer (Fig. 2f).
Claims 3-4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Janisch et al. (US 20180151367 A1).
Regarding claims 3 and 18, Janisch fails to disclose (claim 3) the manufacturing process according to claim 2, wherein the annealing is performed at a temperature higher than 400°C, and (claim 18) the method according to claim 17, wherein the annealing is performed at a temperature higher than 400°C.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select an annealing temperature within the claimed range in Janisch and arrive at the claimed invention so as to ensure proper thermal oxidation within desired thickness ranges is achieved (“range between 100 nm and 500 nm”, [0035]) and achieve a proper buffer layer thickness (“During the thermal oxidation process step the phosphorous of the implantation layer 111 is driven towards the inside of wafer 101 by diffusion to form an n-type layer 108 which will form the buffer layer 108 in the final device”, [0035]) since selection of a given anneal temperature is within the skill set of one of ordinary skill in the art and would have yielded predictable results.
Regarding claim 4, Janisch fails to disclose the manufacturing process according to claim 2, wherein the first doped region has a thickness, along the direction, greater than 2 µm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select a thickness within the claimed range in Janisch and arrive at the claimed invention so as to achieve a proper buffer layer thickness (“During the thermal oxidation process step the phosphorous of the implantation layer 111 is driven towards the inside of wafer 101 by diffusion to form an n-type layer 108 which will form the buffer layer 108 in the final device”, [0035]) since selection of an implanted or diffused layer thickness is within the skill set of one of ordinary skill in the art and would have yielded predictable results.
Claims 3-4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Janisch et al. (US 20180151367 A1) in view of Gao et al. (of record, CN 102693912 B, machine translation provided).
Regarding claims 3 and 18, Janisch fails to disclose (claim 3) the manufacturing process according to claim 2, wherein the annealing is performed at a temperature higher than 400°C, and (claim 18) the method according to claim 17, wherein the annealing is performed at a temperature higher than 400°C.
Gao discloses (claim 3) wherein the annealing is performed at a temperature higher than 400°C, and (claim 18) wherein the annealing is performed at a temperature higher than 400°C ([0040] – “selecting the annealing temperature is 1100 degrees centigrade to 1250 degrees centigrade”).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select an annealing temperature within the claimed range in Janisch in view of Gao and arrive at the claimed invention so as to achieve a dopant distribution with is “beneficial for reducing turn-off loss” (Gao, [0040]).
Regarding claim 4, Janisch fails to disclose the manufacturing process according to claim 2, wherein the first doped region has a thickness, along the direction, greater than 2 µm.
Gao discloses wherein the first doped region has a thickness, along the direction, greater than 2 µm (FS, Fig. 6, 10-40 µm).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to select a thickness within the claimed range in Janisch in view of Gao and arrive at the claimed invention so as to achieve a dopant distribution with is “beneficial for reducing turn-off loss” (Gao, [0040]).
Claims 6 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Janisch et al. (US 20180151367 A1) in view of Tihanyi et al. (US 20070096172 A1).
Regarding claims 6 and 19, Janisch fails to disclose (claim 6) the manufacturing process according to claim 1, further comprising: thinning the work wafer before forming the first doped region, and (claim 19) the method according to claim 17, further comprising: thinning, prior to forming the first doped layer, the wafer.
Tihanyi discloses (claim 6) further comprising: thinning the work wafer (100) before forming the first doped region (13, Fig. 4, [0074] – “This heavily-doped connection zone 13 may, for example, be produced by ion implantation via the rear face, in which case the semiconductor body 100 may be thinned or etched back, preferably starting from the rear face, before implantation of this connection zone”), and (claim 19) the method according to claim 17, further comprising: thinning, prior to forming the first doped layer (13), the wafer (100, Fig. 4, [0074]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the thinning prior to implanting step of Tihanyi in Janisch and arrive at the claimed invention so as to allow for formation of high doped regions in a rear of a substrate (Tihanyi, [0074]) and allow for removal of imperfections prior to said implanting.
Examiner Note
No prior art is applied to claim 10.
The prior art of record fails to disclose or suggest “further comprising: bonding a first temporary support body on the first side of the work wafer, before forming the first doped region; bonding a second temporary support body on the second side of the work wafer, before forming the device active region; and removing the first temporary support body before forming the device active region”.
The claim is not objected as including allowable subject matter because the claim is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement given their dependence from claim 1; see 35 USC rejection above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
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