Prosecution Insights
Last updated: July 17, 2026
Application No. 18/191,867

Component Carrier With Reinforcement Layer Structure and Manufacturing Method Using Two Temporary Carriers

Final Rejection §102§103
Filed
Mar 28, 2023
Examiner
CHANG, JAY C
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
At&S Austria Technologie & Systemtechnik AG
OA Round
2 (Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
564 granted / 663 resolved
+17.1% vs TC avg
Moderate +14% lift
Without
With
+14.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
31 currently pending
Career history
697
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
58.6%
+18.6% vs TC avg
§102
18.9%
-21.1% vs TC avg
§112
19.9%
-20.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 663 resolved cases

Office Action

§102 §103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This action is responsive to the following communications: the Amendment filed 4/1/2026. Claims 1-20 are pending. Claims 11-20 are withdrawn. Claim 1 is currently amended. Claim 1 is independent. Response to Arguments Applicants' arguments and amendments, filed 4/1/2026, with respect to independent claim 1, although substantive and pertinent to expediting the prosecution of the current application, are considered not persuasive, respectfully, for the reasons that follow. Regarding independent claim 1, the claim has been amended to recite “wherein one of the at least one electrically insulating layer structures is configured as a core layer structure, and wherein the thickness of the component is essentially equal to or less than that of the core layer structure”, which applicants contend is not disclosed or taught by the prior art, including Kim, since Kim does not disclose a single core layer structure but rather a plurality of stacked cores layers 114a and 114b (Remarks 11-12). Applicants’ contentions are fully considered, however are not found persuasive, since as noted below in the rejection of independent claim 1 Figure 1A of Kim discloses wherein one of the at least one electrically insulating layer structures 114 is configured as a core layer structure 114 (collectively the stack of 114 layers), and wherein the thickness of the component 120 is essentially equal to or less than that of the core layer structure 114. Claim 1, as currently written, does not expressly require that the claimed “core layer structure” consists of only one of the at least one electrically insulating layer structures such that it is only a single integrated layer structure. Thus, it is considered proper to interpret the claimed “core layer structure” as the collective stack of 114 layers in Figure 1A of Kim. Thus, for the aforementioned reasons the rejection is deemed proper. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-6 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2022/0102236 A1, hereinafter “Kim”). Regarding independent claim 1, Figure 1A of Kim discloses a component carrier, comprising: a stack 110 (“connection layer”- ¶0025) having at least one electrically insulating layer structure 114 (“core… insulating material”- ¶0030) and at least one electrically conductive layer structure 116 (“conductive pads”- ¶0026); a component 120 (“chip”- ¶0025), partially embedded in one of the at least one electrically insulating layer structure 114 of the stack 110, wherein component connection pads 122 (“pad”- ¶0032) provided at a first main surface of the component 120 are flush with a first main surface of one of the at least one electrically insulating layer structures 114; and a reinforcement layer structure 190 (“layer”- ¶0025, which is physically attached to the surrounding elements such that it would physically support/reinforce the surrounding elements to a certain extent), provided over a second main surface of one of the at least one electrically insulating layer structures 114, opposed to the first main surface of one of the at least one electrically insulating layer structures 114. wherein one of the at least one electrically insulating layer structures 114 is configured as a core layer structure 114 (collectively the stack of 114 layers), and wherein the thickness of the component 120 is essentially equal to or less than that of the core layer structure 114. Regarding claim 2, Figure 1A of Kim discloses wherein the reinforcement layer structure 190 comprises a reinforcement dielectric layer structure 192 (“insulation layer”- ¶0044). Regarding claim 3, Figure 1A of Kim discloses wherein the reinforcement layer structure 190 comprises at least one of: a fully cured resin, a fiber-reinforced resin a prepreg, a fiber-free reinforced resin, an insulation film 192 (“insulation layer”- ¶0044), a fiber-free resin. Regarding claim 4, Figure 1A of Kim discloses wherein the reinforcement layer structure 190 comprises a first reinforcement electrically conductive layer structure 196b (“conductive via”- ¶0045) sandwiched between two reinforcement dielectric layer structures 192b, 192c (“insulation layer”- ¶0045). Regarding claim 5, Figure 1A of Kim discloses wherein the reinforcement layer structure 190 comprises a reinforcement dielectric layer structure 192c (“insulation layer”- ¶0045) sandwiched between a first and a second reinforcement electrically conductive layer structure 198b, 198c (“heat dissipation pad”- ¶0046). Regarding claim 6, Figure 1A of Kim discloses wherein at least one reinforcement electrically conductive layer structure 198c (“heat dissipation pad”- ¶0046) is patterned, the patterned reinforcement electrically conductive layer structure 198c comprising a thermal dissipation structure (¶0046). Regarding claim 9, Figure 1A of Kim discloses wherein at least one further electrically insulating layer structure 162 (“insulation layer”- ¶0040) is provided on the first main surface of the at least one electrically insulating layer structure 114. Regarding claim 10, Figure 1A of Kim discloses the component carrier further comprising: a redistribution layer structure 160 (“redistribution layer”- ¶0041), provided on the at least one electrically insulating layer structure 114, coupled to the first main surface of the embedded component 120. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Kim. Regarding claim 7, Figure 1A of Kim discloses wherein the component 120 comprises a thickness. Kim does not expressly disclose wherein the thickness of the component 120 is 100 µm or smaller. However, it would have been obvious to form the thickness of the component within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Regarding claim 8, Figure 1A of Kim discloses wherein the core layer structure 114 comprises a thickness thicker than the component 120. Kim does not expressly disclose wherein the core layer structure is 30 µm to 50 µm thicker than the component. However, it would have been obvious to form the core layer structure such that it is thicker than the component by the thickness within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JAY C CHANG/ Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 28, 2023
Application Filed
Nov 10, 2025
Non-Final Rejection (signed) — §102, §103
Jan 02, 2026
Non-Final Rejection mailed — §102, §103
Apr 01, 2026
Response Filed
Apr 23, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+14.1%)
2y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 663 resolved cases by this examiner. Grant probability derived from career allowance rate.

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