DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-7, 9, 17, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Huang et al. US 12,260,161 B2 (“Huang”).
As to claim 1, Huang discloses a method comprising:
executing a plurality of design iterations for a design flow for a circuit; wherein:
the design flow comprises a sequence of at least two stages, and each stage produces an output design of the circuit from an input design of the circuit in accordance with parameters for that stage (Figure 10 or Column 13 Line 7-Column 14 Line 2 – e.g., multiple iterations of synthesis/place and route/STA steps with component parameters according to design specifications);
the design iterations comprise selecting parameter values for slices of one or more stages of the design flow (Figure 10 or Column 13 Line 41-Column 14 Line 2 – e.g., updating/selecting “plurality of component parameters”); and
the design iterations for a first one of the slices comprise selecting parameter values for a non-final stage of the design flow based on a final quality of result (QoR) of the design flow (Figure 10 or Column 13 Line 41-Column 14 Line 2 – e.g., updating/selecting is performed in order to have performance simulation results meet a circuit design specification); and
adapting, by a processing device, the design iterations for the first slice based on final QoRs produced by the design iterations (Figure 10 or Column 13 Line 7-Column 14 Line 2 – e.g., further iterations of synthesis/place and route/STA steps build on previous design iterations).
As to claim 2, Huang discloses the method of claim 1. Huang further discloses wherein the design iterations comprise selecting parameter values for each of the non-final stages of the design flow based on the final QoR of the design flow (Figure 10 or Column 13 Line 41-Column 14 Line 2 – e.g., updating/selecting is performed in order to have performance simulation results meet a circuit design specification).
As to claim 3, Huang discloses the method of claim 2. Huang further discloses adapting the design iterations that select parameter values based on the final QoR of the design flow, based on final QoRs produced by the design iterations (Figure 10 or Column 13 Line 7-Column 14 Line 2 – e.g., further iterations of synthesis/place and route/STA steps build on previous design iterations).
As to claim 5, Huang discloses the method of claim 1. Huang further discloses wherein the final QoR comprises an aggregate of at least two performance metrics of the output design of the circuit from a final stage of the design flow (Figure 2 or Column 6 Line 36—44 – e.g., a simulation result according to multiple performance simulation results).
As to claim 6, Huang discloses the method of claim 1. Huang further discloses wherein the design iterations for the first slice select parameter values for all stages in the first slice based on the final QoR of the design flow (Figure 10 or Column 13 Line 41-Column 14 Line 2 – e.g., updating/selecting is performed in order to have performance simulation results meet a circuit design specification).
As to claim 7, Huang discloses the method of claim 1. Huang further discloses wherein adapting the design iterations for the first slice is further based on final QoRs produced by design iterations for other slices (Figure 10 or Column 13 Line 7-Column 14 Line 2 – e.g., further iterations of synthesis/place and route/STA steps build on previous design iterations).
Claims 9 and 17 recite elements similar to claim 1, and are rejected for the same reasons.
As to claim 20, Huang discloses the method of claim 17. Huang further discloses wherein adapting the final QoR-based design iterations uses machine learning (Column 7 Lines 54-63 or Column 9 Line 54-Column 10 Line 14).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10, 11, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 9 above, and further in view of Formato US 2012/0331436 A1 (“Formato”).
As to claim 10, Huang discloses the method of claim 9. Huang does not explicitly disclose the additional elements of claim 10. However, the missing element is well known in the art because while teaching an optimization method involving iterations of specifying parameters, Formato discloses the use of iteration termination criteria (Formato Paragraph 10), including a number of iterations (Formato Paragraph 45). The examiner notes that an iteration number is directly related to the amount of computation the method requires. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the instructions specify compute limits on the design iterations because doing so would allow the method to be completed in a predictable amount of time.
As to claim 11, Huang discloses the method of claim 9. Huang does not explicitly disclose the additional elements of claim 11. However, the missing element is well known in the art because while teaching an optimization method involving iterations of specifying parameters, Formato discloses the use of iteration termination criteria (Formato Paragraph 10), including a variety of different criteria (Formato Paragraph 45). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the instructions specify stop rules for early termination of design iterations because doing so would allow the method to be completed in a smaller amount of time.
As to claim 13, Huang discloses the method of claim 9. Huang does not explicitly disclose the additional elements of claim 13. However, the missing element is well known in the art because while teaching an optimization method involving iterations of specifying parameters, Formato discloses the use of iteration termination criteria (Formato Paragraph 10), including a number of iterations (Formato Paragraph 45). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the instructions specify limits on a number of design iterations that are executed because doing so would allow the method to be completed in a predictable amount of time.
Allowable Subject Matter
Claims 4, 8, 12, 14-16, 18, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a method/system/non-transitory CRM having the combination of step/elements in the claims including, among other elements, the stage and QoR and design flow details of the claims, in combination with the design iteration and adaption details of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851