Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-14, 21-26 in the reply filed on 11/11/25 is acknowledged.
Information Disclosure Statement
The information disclosure statements filed 2/2/24 have been considered.
Oath/Declaration
Oath/Declaration filed on 6/1/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7-14 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Yu et al. (U.S. Patent Publication No. 2021/0407942).
Referring to figures 1-45, Yu et al. teaches a method comprising:
attaching a back-side of a first die (75) to a front-side of a wafer (155), the wafer comprising a substrate (152) and a transistor (154) along the substrate, the transistor facing the front-side of the wafer, the first die (75) comprising:
a first bond pad (136) along the back-side of the first die;
a first back-side interconnect structure (100) adjacent and electrically connected to the first bond pad;
a first front-side interconnect structure (80) adjacent and electrically connected to the first back-side interconnect structure;
a first semiconductor substrate (72) interposed between the first back-side interconnect structure and the first front-side interconnect structure; and
a first transistor (74) along the first semiconductor substrate (72), the first transistor facing the front-side of the first die;
forming a second bond pad (96) over the first front-side interconnect structure; and
attaching a second front-side of a second die (55) to the second bond pad (96) of the first die, the second die comprising a second semiconductor substrate and a second transistor, the second transistor facing the front-side of the second die (see figures 19).
Regarding to claim 7, forming the second bond pad is after attaching the back-side of the first die to the front-side of the wafer (see figures 19).
Regarding to claim 8, attaching a carrier (52) to a back-side of the second die; thinning the substrate along a back-side of the wafer (see figures 15-16); and forming a back-side interconnect structure on the back-side of the wafer (190, see figures 18-19).
Regarding to claim 9, a method comprising:
forming a first die (75), forming the first die comprising:
forming a first conductive via (82/100c) in a front-side of a substrate;
forming a transistor (73) comprising a gate electrode and a source/drain region over the front-side of the substrate (see figure 19);
forming a first interconnect structure (80) over the front-side of the substrate (72), the first interconnect structure being electrically connected to the gate electrode (see figure 19);
forming a second conductive via (125) in a back-side of the substrate, the second conductive via being connected to the source/drain region; and
forming a second interconnect structure (100) over the back-side of the substrate;
attaching the first die (75) to a wafer (155), the wafer and the first die being electrically connected; and
attaching a second die (55) to the first die, the first die being electrically interposed between the wafer and the second die (see figure 19).
Regarding to claim 10, an active side of the second die (55) faces the front-side of the substrate of the first die (75, see figure 19).
Regarding to claim 11, after attaching the second die (55) to the first die (75): forming a third interconnect structure (190) over a back-side of the wafer; and forming external connectors (191) over the third interconnect structure and over the back-side of the wafer (see figures 18-19).
Regarding to claim 12, forming the first die (75) comprises forming a plurality of first dies at a wafer level, wherein attaching the first die to the wafer comprises attaching the plurality of first dies to the wafer, wherein after attaching the second die (55/215) to the first die (75), the second die is electrically connected to each die of the plurality of first dies (see figure 19b).
Regarding to claim 13, attaching the second die to the first die comprises attaching a plurality of second dies to the first die, and wherein each die of the plurality of second dies is electrically connected to the first die (see figure 19).
Regarding to claim 14, forming the first die (75) comprises forming a plurality of first dies at a wafer level, further comprising attaching an additional first die to the first die, wherein the first die is electrically interposed between the wafer and the additional first die, and wherein attaching the second die to the first die comprises attaching the second die to the additional first die (see figure 19).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 2-3, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Patent Publication No. 2021/0407942) applied in claim(s) 1, 7-14 above in view of Yeh et al. (U.S. Patent Publication No. 2024/0047417) and Syue et al. (U.S. Patent Publication No. 2023/0377949).
Referring to figures 1-45, Yu et al. teaches a method comprising: attaching a back-side of a first die (75) to a front-side of a wafer (155), the wafer comprising a substrate (152) and a transistor (154) along the substrate, the transistor facing the front-side of the wafer, the first die (75) comprising:
a first bond pad (136) along the back-side of the first die;
a first back-side interconnect structure (100) adjacent and electrically connected to the first bond pad;
a first front-side interconnect structure (80) adjacent and electrically connected to the first back-side interconnect structure;
a first semiconductor substrate (72) interposed between the first back-side interconnect structure and the first front-side interconnect structure; and
a first transistor (74) along the first semiconductor substrate (72), the first transistor facing the front-side of the first die;
forming a second bond pad (96) over the first front-side interconnect structure; and
attaching a second front-side of a second die (55) to the second bond pad (96) of the first die, the second die comprising a second semiconductor substrate and a second transistor, the second transistor facing the front-side of the second die (see figures 19).
However, the reference does not clearly teach the first die comprises a first type of conductive via and a second type of conductive via extending through the first semiconductor substrate, wherein a width of the first type of conductive via decreases in a direction from the front-side of the first die to the back-side of the first die, and wherein a width of the second type of conductive via decreases in a direction from the back-side of the first die to the front-side of the first die (in claim 2), the first type of conductive via comprises a first via and a second via, wherein the first via extends from a front-side of the first semiconductor substrate to a back-side of the first semiconductor substrate, and wherein the second via extends from the first front-side interconnect structure to the back-side of the first semiconductor substrate (in claim 3), the first type of conductive via is wider than the second type of conductive via (in claim 6).
Yeh et al. teaches a the first die comprises a first conductive via and a second conductive via extending through the first semiconductor substrate, wherein a width of the first conductive via decreases in a direction from the front-side of the first die to the back-side of the first die, and wherein a width of the second conductive via decreases in a direction from the back-side of the first die to the front-side of the first die (in claim 2), the first conductive via is wider than the second conductive via (42, see figure 8, in claim 6). It would have been obvious to one of ordinary skill in the art to form the conductive via, wherein a width of the first conductive via decreases in a direction from the front-side of the first die to the back-side of the first die, and wherein a width of the second conductive via decreases in a direction from the back-side of the first die to the front-side of the first die (in claim 2), the first conductive via is wider than the second conductive via as taught by the Yeh et al. in the device formed by the Yu et al. It is well settled that, the change in shape was a matter of design choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the trench was significant. In re Dailey, 357 F.2d 669, 149 USPTO 47 (CCPA 1996).
And Syue et al. teaches a stacked structures having first type of conductive via and a second type of conductive via extending through the first semiconductor substrate (meeting claims 2, 3, see figure 8, paragraphs# 30-31).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a semiconductor with in Yu et al. as taught by Yeh et al. and Syue et al. because it is known in the semiconductor art to form conductive vias with desired conductivity.
Allowable Subject Matter
Claims 21-26 are allowed. None of the prior art teaches or suggest forming a third via through the interlayer dielectric to the buried contact; forming a first interconnect structure over and electrically connected to the first transistor, the second via, and the third via, forming a fourth via through the back-side of the first semiconductor substrate and to the buried contact;
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Because none of the prior art teaches or suggests the second type of conductive via comprises a third via and a fourth via, and wherein the third via extends from the back-side of the first semiconductor substrate and is electrically coupled to a buried contact embedded in the front- side of the first semiconductor substrate.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893