DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 7, 9, and 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singhal et al, US Patent Application Publication 2022/0123114 (as cited in previous Office Action)
Regarding claim 1, Singhal teaches a semiconductor processing method comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber, wherein a substrate 411 (figure 4A) is disposed within the processing region, and wherein the deposition precursors comprise a silicon-containing precursor (claim 9, lines 2-5);
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5 and claim 11);
generating plasma effluents of the deposition precursors and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate (doped polysilicon layer, claim 9, lines 6-8),
wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Regarding claims 2-4, Singhal teaches the silicon-containing precursor comprises tetraethyl orthosilicate (TEOS) [0065], wherein the deposition precursors further comprise an oxygen-containing precursor [0065], and the oxygen-containing precursor comprises nitrous oxide (N2O) [0065].
Regarding claims 6-7, Singhal teaches the silicon-containing material is characterized by a leakage current of less than or about 5.0E-08 A/cm2 at 9 MV/cm [0068] and the silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV/cm at 0.001 A/cm2 [0069].
Regarding claims 9-10, Singhal teaches annealing the silicon-containing material, and annealing the silicon-containing material comprises exposing the silicon-containing material to a temperature of greater than or about 600 °C [0076].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 8, and 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Singhal et al, US Patent Application Publication 2022/0123114 (as cited in previous Office Action)
Regarding claims 5 and 8, Singhal fails to teach deposition precursors and the dopant precursor are generated at a plasma power less than or about 2000 W and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 11, Singhal teaches a semiconductor processing method comprising:
providing a silicon-containing precursor (claim 9, line 2-5) and an oxygen-containing precursor [0065] to a processing region of a semiconductor processing chamber, wherein a substrate 411 (figure 4A) is disposed within the processing region;
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5);
generating plasma effluents of the silicon-containing precursor, the oxygen-containing precursor, and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate (doped polysilicon layer, claim 9, lines 6-8), wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Singhal fails to teach the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 12-13, Singhal teaches the dopant precursor comprises phosphine (PH3) [0052], wherein a flow rate of the dopant precursor is less than or about 500 sccm [0053].
Regarding claim 14, Singhal fails to teach the silicon-containing material is characterized by a phosphorous content of less than or about 5 at.%.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 15,Singhal teaches the silicon-containing material 145b is deposited on a polysilicon material 145a (figure 4C).
Regarding claim 16, Singhal teaches annealing the silicon-containing material at a temperature of greater than or about 600 °C [0076], but fails to teach annealing for greater than or about 5 minutes.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 17, Singhal fails to teach subsequent annealing, a phosphorous content in the silicon-containing material decreases by less than or about 1.0 at.%.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 18, Singhal a semiconductor processing method comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber (claim 9, line 2-5), wherein a substrate 411 (figure 4A) is disposed within the processing region;
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5 and claim 11);
generating plasma effluents of the deposition precursors and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate,
wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Singhal fails to teach the silicon-containing material is characterized by a phosphorus content of less than or about 3 at.% and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 19 and 20, Singhal teaches the silicon-containing material comprises phosphorous doped silicon oxide (claims 9, 11, and [0065]), wherein: the silicon-containing material is characterized by a leakage current of less than or about 1.0E-09 A/cm2 [0068]; and the silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV/cm at 0.001 A/cm2 [0069].
Response to Arguments
Applicant's arguments filed 25 November 2025 have been fully considered but they are not persuasive.
In response to Applicant’s argument that it is not clear that the cumulative stress of the semiconductor layers 415a-c of Singhal would be, it is noted that since the reference of Singhal teaches the stress levels of individual portions of layers 415a, 415b or 415c, it is noted that knowing the cumulative stress of the semiconductor layers 415a-c is not necessary since all of the layers meet the claimed limitation of having “a stress of greater than or about – 50 MPa”.
In response to Applicant’s argument that Singhal only provides positive stress values, wherein independent claims 1, 11, and 18 recites stresses as more negative stress, it is noted that since the claim recites the limitation that “a stress of greater than or about – 50 MPa”, it is noted that a positive stress values would be greater that a negative value stress level and meet the limitation of the claim. Therefore, having a stress levels recited in [0062] of Singhal would then meet the limitations of this claim.
Therefore, the rejection of these claims using the cited prior art of Singhal is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899