DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4 June 2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Singhal et al, US Patent Application Publication 2022/0123114 (as cited in previous Office Action) in view of Mikata et al, US Patent 6,713,824 (newly submitted)
Regarding claim 1, Singhal teaches a semiconductor processing method comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber, wherein a substrate 411 (figure 4A) is disposed within the processing region, and wherein the deposition precursors comprise a silicon-containing precursor (claim 9, lines 2-5);
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5 and claim 11);
generating plasma effluents of the deposition precursors and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate (doped polysilicon layer, claim 9, lines 6-8),
wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Singhal fails to teach the stress value that is more negative means the silicon-containing material has greater stress.
However, Mikata teaches that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer. Mikata teaches that forming a polysilicon layer at 620 oC results in a tensile stress-film of about -300 MPa (see column 5, lines 62-64)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mikata with that of Singhal because it is generally-known in the art that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer
Regarding claims 2-4, Singhal teaches the silicon-containing precursor comprises tetraethyl orthosilicate (TEOS) [0065], wherein the deposition precursors further comprise an oxygen-containing precursor [0065], and the oxygen-containing precursor comprises nitrous oxide (N2O) [0065].
Regarding claims 5 and 8, Singhal fails to teach deposition precursors and the dopant precursor are generated at a plasma power less than or about 2000 W and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 6-7, Singhal teaches the silicon-containing material is characterized by a leakage current of less than or about 5.0E-08 A/cm2 at 9 MV/cm [0068] and the silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV/cm at 0.001 A/cm2 [0069].
Regarding claims 9-10, Singhal teaches annealing the silicon-containing material, and annealing the silicon-containing material comprises exposing the silicon-containing material to a temperature of greater than or about 600 °C [0076].
Regarding claim 11, Singhal teaches a semiconductor processing method comprising:
providing a silicon-containing precursor (claim 9, line 2-5) and an oxygen-containing precursor [0065] to a processing region of a semiconductor processing chamber, wherein a substrate 411 (figure 4A) is disposed within the processing region;
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5);
generating plasma effluents of the silicon-containing precursor, the oxygen-containing precursor, and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate (doped polysilicon layer, claim 9, lines 6-8), wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Singhal fails to teach the stress value that is more negative means the silicon-containing material has greater stress and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, Mikata teaches that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer. Mikata teaches that forming a polysilicon layer at 620 oC results in a tensile stress-film of about -300 MPa (see column 5, lines 62-64)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mikata with that of Singhal because it is generally-known in the art that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer
Singhal and Mikata fail to teach the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 12-13, Singhal teaches the dopant precursor comprises phosphine (PH3) [0052], wherein a flow rate of the dopant precursor is less than or about 500 sccm [0053].
Regarding claim 14, Singhal fails to teach the silicon-containing material is characterized by a phosphorous content of less than or about 5 at.%.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 15,Singhal teaches the silicon-containing material 145b is deposited on a polysilicon material 145a (figure 4C).
Regarding claim 16, Singhal teaches annealing the silicon-containing material at a temperature of greater than or about 600 °C [0076], but fails to teach annealing for greater than or about 5 minutes.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 17, Singhal fails to teach subsequent annealing, a phosphorous content in the silicon-containing material decreases by less than or about 1.0 at.%.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 18, Singhal a semiconductor processing method comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber (claim 9, line 2-5), wherein a substrate 411 (figure 4A) is disposed within the processing region;
providing a dopant precursor to the processing region of the semiconductor processing chamber, wherein the dopant precursor comprises a phosphorous-containing precursor (claim 9, line 5 and claim 11);
generating plasma effluents of the deposition precursors and the dopant precursor (generation of plasma from deposition precursors, see [0051]); and
depositing a silicon-containing material 415a, 415b, 415c (figure 4A) on the substrate,
wherein the silicon-containing material is characterized by a stress of greater than or about – 50 MPa [0062].
Singhal fails to teach the silicon-containing material is characterized by a phosphorus content of less than or about 3 at.%, the stress value that is more negative means the silicon-containing material has greater stress, and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, Mikata teaches that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer. Mikata teaches that forming a polysilicon layer at 620 oC results in a tensile stress-film of about -300 MPa (see column 5, lines 62-64)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Mikata with that of Singhal because it is generally-known in the art that doped polysilicon made contains either compressive stress or tensile stress and is dependent upon the deposition temperature of the polysilicon layer.
Singhal and Mikata fail to teach the silicon-containing material is characterized by a phosphorus content of less than or about 3 at.% , and the silicon-containing material is characterized by a wet etch rate ratio (WERR) of greater than or about 2.0.
However, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claims 19 and 20, Singhal teaches the silicon-containing material comprises phosphorous doped silicon oxide (claims 9, 11, and [0065]), wherein: the silicon-containing material is characterized by a leakage current of less than or about 1.0E-09 A/cm2 [0068]; and the silicon-containing material is characterized by a breakdown voltage of greater than or about 6.0 MV/cm at 0.001 A/cm2 [0069].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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