DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/31/26 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rajagopalan et al. (US PGPub 2024/0018643, hereinafter referred to as “Rajagopalan”) in view of Chen et al. (US PGPub 2022/0282389, hereinafter referred to as “Chen”).
Rajagopalan teaches the semiconductor structure as claimed. See figures 1A-16 and corresponding text, where Rajagopalan teaches, in claim 1, a back side metallization thin film structure, comprising:
a wafer (1400), wherein a plurality of integrated circuit devices are formed on a front side of the wafer (1400); (figure 14; [0044]) and
a metallic nano-twinned thin film (1300/1200) formed directly on a back side of the wafer (1400), wherein the metallic nano-twinned thin film comprises silver, copper, gold, palladium, or nickel (teaches nickel nano-twinned thin structure [0044]), wherein the metallic nano-twinned thin film (1300/1200) comprises a transition layer (1300) near the wafer and a twin layer (1200) away from the wafer (1400), the twin layer accounts for at least 70% of a thickness of the metallic nano-twinned thin film (1300/1200) and comprises parallel-arranged twin boundaries, an average distance between the parallel-arranged twin boundaries is 1 nm to 100 nm (figure 14; [0044-0045]), and the parallel-arranged twin boundaries comprise no less than 50% of (111) crystal orientation (figure 2B; [0033]); wherein the metallic nano-twinned thin film covers more than 90% of the surface area of the back side of the wafer (figure 14; [0044]).
However, Rajagopalan fails to explicitly show, in claim 1, wherein the wafer is a 6-inch wafer, an 8-inch wafer, or a 12-inch wafer.
Chen teaches, in claim 1, a similar semiconductor device that includes a wafer that is for example 12-inch silicon wafer ([0050]). In addition, Chen provides the advantages of providing high electrical conductivity and high thermal conductivity that can be applied to various electronic components ([0010]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the wafer is a 6-inch wafer, an 8-inch wafer, or a 12-inch wafer, in the device of Rajagopalan, according to the teachings of Chen, with the motivation of providing high electrical conductivity and high thermal conductivity that can be applied to various electronic components.
Rajagopalan in view of Chen teaches, in claim 5, wherein the metallic nano-twinned thin film comprises nano-twinned pillars, wherein a diameter of the nano-twinned pillars is between 0.01µm and 10µm (figure 15; [0045], Rajagopalan).
Rajagopalan in view of Chen teaches, in claim 6, wherein a thickness of the metallic nano-twinned thin film is between 0.01µm and 10 µm (figure 15; [0045], Rajagopalan).
Rajagopalan in view of Chen teaches, in claim 7, wherein the wafer comprises a single crystal of silicon, silicon carbide, gallium arsenide, or sapphire (figure 14; [0044], Rajagopalan).
Rajagopalan in view of Chen teaches, in claim 8, wherein the metallic nano-twinned thin film substantially covers an entirety of the back side of the wafer (figure 1B; [0030], Rajagopalan).
Rajagopalan in view of Chen teaches, in claim 11, further comprising a substrate bonded to the back side of the wafer through the metallic nano-twinned thin film ([0004], Rajagopalan).
Rajagopalan in view of Chen teaches, in claim 12, wherein the integrated circuit devices are power devices ([0010], Chen).
Conclusion
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/STANETTA D ISAAC/ Examiner, Art Unit 2898 September 4, 2026
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