DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 2/11/26. Currently, claims 1-8 and 11-19 are pending. Claims 11-19 are withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-8, 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US PGPub 2021/0225793, hereinafter referred to as “Tsai”) in view of Chen et al. (US PGPub 2022/0282389, hereinafter referred to as “Chen”).
Tsai discloses the semiconductor device substantially as claimed. See figures 1A-7C and corresponding text, where Tsai teaches, in claim 1, a back side metallization thin film structure, comprising:
a wafer (10), wherein a plurality of integrated circuit devices are formed on a front side of the wafer (10); and
a metallic nano-twinned thin film (20) on a back side of the wafer (10), wherein the metallic nano-twinned thin film comprises silver, copper, gold, palladium, or nickel (teaches silver nano-twinned thin structure for low-temperature and low-pressure wafer bonding and 3D-IC flip-chip assembly [0024], is on back side of the wafer), wherein the metallic nano-twinned thin film (20) comprises a transition layer near the wafer and a twin layer (14) away from the wafer (10), the twin layer accounts for at least 70% of a thickness of the metallic nano-twinned thin film (20) (the examiner views that having a metallic nano-twinned thin film that is 100% of a thickness would not be precluded, thus the twin layer (14) encompasses 100% the thickness and 0% of the transition layer) and comprises parallel-arranged twin boundaries, an average distance between the parallel-arranged twin boundaries is 1 nm to 100 nm (figure 1B; [0030]), and the parallel-arranged twin boundaries comprise no less than 50% of (111) crystal orientation (figure 1B; [0030]); wherein the metallic nano-twinned thin film covers more than 90% of the surface area of the back side of the wafer (figure 1B; [0030]).
However, Tsai fails to explicitly show, in claim 1, wherein the wafer is a 6-inch wafer, an 8-inch wafer, or a 12-inch wafer.
Chen teaches, in claim 1, a similar semiconductor device that includes a wafer that is for example 12-inch silicon wafer ([0050]). In addition, Chen provides the advantages of providing high electrical conductivity and high thermal conductivity that can be applied to various electronic components ([0010]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the wafer is a 6-inch wafer, an 8-inch wafer, or a 12-inch wafer, in the device of Tsai, according to the teachings of Chen, with the motivation of providing high electrical conductivity and high thermal conductivity that can be applied to various electronic components.
Tsai in view of Chen teaches, in claim 2, further comprising an adhesive layer (12) disposed between the wafer and the metallic nano-twinned thin film (figure 2C; [0054], Tsai).
Tsai in view of Chen teaches, in claim 3, wherein a thickness of the adhesive layer is between 0.01 µm and 1 µm ([0049], Tsai).
Tsai in view of Chen teaches, in claim 4, wherein the adhesive layer comprises titanium, chromium, aluminum, or a combination thereof ([0049], Tsai).
Tsai in view of Chen teaches, in claim 5, wherein the metallic nano-twinned thin film comprises nano-twinned pillars, wherein a diameter of the nano-twinned pillars is between 0.01µm and 10µm (figure 1B; [0031], Tsai).
Tsai in view of Chen teaches, in claim 6, wherein a thickness of the metallic nano-twinned thin film is between 0.01µm and 10 µm (figure 1B; [0031], Tsai).
Tsai in view of Chen teaches, in claim 7, wherein the wafer comprises a single crystal of silicon, silicon carbide, gallium arsenide, or sapphire (figure 1A; [0026], Tsai).
Tsai in view of Chen teaches, in claim 8, wherein the metallic nano-twinned thin film substantially covers an entirety of the back side of the wafer (figure 1B; [0030], Tsai).
Tsai in view of Chen teaches, in claim 11, further comprising a substrate bonded to the back side of the wafer through the metallic nano-twinned thin film ([0024], teaches silver nano-twinned thin structure for low-temperature and low-pressure wafer bonding and 3D-IC flip-chip assembly).
Tsai in view of Chen teaches, in claim 12, wherein the integrated circuit devices are power devices ([0010], Chen).
Response to Arguments
Applicant's arguments filed 2/11/26 have been fully considered but they are not persuasive. In the remarks applicant raises the clear issue as to whether Tsai alone or in combination with Chen suggests or renders obvious wherein the wafer is a 6-inch wafer, an 8-inch wafer, or a 12-inch wafer, and the metallic nano-twinned thin film covers more than 90% of the surface area of the back side of the wafer.
The examiner views that Tsai in view of Chen does suggest that the metallic nano-twinned thin film covers the surface area of the back side of a wafer. Specifically, Tsai teaches forming the metallic nano-twinned thin film used to improve the bonding surface of the semiconductor device for 3D-IC flip-chip assembly ([0024]) for solder reflow bonding ([0044]), thus conventionally includes the backside of the wafer or chip. In addition, Tsai shows a cross-sectional of the bonding film where the metallic nano-twinned thin film (14) overlaps and covers the underlying layers bonded to the substrate (10), thus at least 90% of the surface is covered (figure 2C; [0054-0055]). Lastly, Tsai only fails to show the size of the wafers, where Chen provides a teaching of a conventional 12 inch wafer size that includes the formation of nano-twinned material, and the advantages of creating high electrical conductivity and high thermal conductivity that can be applied to various electronic components.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 26, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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