DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement has been made to the amendment received on 12/03 /2025. Claims 1-15 and 21-25 are pending in this application. Claims 16-20 are cancelled.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant's election with traverse of Group I, claims 1-15 and new claims 21-25, in the reply filed on 12/03/2025 is acknowledged. The traversal is on the ground that "the Office has failed to demonstrate that a serious search or examination burden would be placed upon the Office if the election was not required". However, this is not found persuasive because as set forth in the restriction requirement dated on 10/03/2025, the device recited in claim 16 can be manufactured by different and materially distinct process. Accordingly, claims 1-15 and claims 16-20 do not pertain to a single inventive concept and therefore were properly grouped as separate inventions; also, Applicant did not provide any evidence that there would not be serious burden when examining claims directed to all of the groups. The requirement is still deemed proper and is therefore made FINAL. Therefore, claims 1-15 and new claims 21-25 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C.103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-7, 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US20230093101A1) in view of Liao et al (US 20210336063A1).
Re claim 1 A method, comprising (2A-11A) [0037]:
forming a plurality of semiconductor sheets (nanosheet stack 305, fig 3A/5A and fig1) [0043] on a front side of a semiconductive layer (semiconductor layer, fig 1) [0049] (semiconductive layer is the top portion of the substrate100 above the bottom surface 815 as defined in para [0061] (fig 8A);
forming a gate strip (dummy gates 405-1, 405-2, 405-3, fig 1 and 4A) [0047] surrounding each at least one of the semiconductor sheets (nanosheet stack 305, fig1/fig 4A) [0047];
forming a plurality of source/drain structures (source/drain regions 620-1,620-2, fig 2) [0051] on either side of each at least one of the semiconductor sheets (nanosheet stack 305, fig 2);
Xie does not teach doping the semiconductive layer with a dopant yielding a doped semiconductive layer, the dopant has a same conductivity type as conductivity type of the source/drain structures and forming a power supply voltage line on a back side of the doped semiconductive layer.
Liao teaches “forming doped regions (n-type region and P-type, fig 19A) [0020] on the semiconductor layer ( 50, fig 19) [0020] with a dopant [0020]; n-type or p-type, the dopant (p-type or n-type) has a same conductivity type as the source/drain structures (“ the n-type region 50N can be for forming n-type devices such as NMOS transistors, and the p-type region 50P can be for forming p-type devices such as PMOS transistor “) [0020], and because n-type devices and p-type devices comprises with n-type and p-type source/drain regions, respectively, the dopants in the doped regions have the same conductivity type as the source /drain structures) and forming a power supply voltage line (144/144P, fig20) [0091] on a back side of the doped semiconductive layer (50, fig 19/20) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught Liao into the structure Xie of to include doping the semiconductive layer with a dopant yielding a doped semiconductive layer, the dopant has a same conductivity type as conductivity type of the source/drain structures and forming a power supply voltage line on a back side of the doped semiconductive layer as claimed.
The ordinary artisan would have been motivated to modify Xie based on the teaching of Liao in the above manner for the purpose of building circuit incorporating both n-type and p-type transistors in a compact form.
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Re claim 4 Xie in view of Liao teach the method of claim 1, wherein the semiconductive layer(semiconductive layer, fig 1A) is in contact with one of the source/drain structures (620-1, fig 11A) [Xie 0047].
Re claim 5. Xie in view of Liao teach the method of claim 1, further comprising: after forming the gate strip (dummy gates 405-1, 405-2, 405-3, fig 1 and 4A) [Xie, 0047] and prior to forming the source/drain structures (source/drain regions 620-1,620-2, fig 6) [0051], forming a dielectric layer (605-1, 2 fig 2) on the front side of the semiconductive layer and at a first side of the gate strip ( 405-1, 405-2, 403, fig 6) [Xie, 0047].
Re claim 6 Xie in view of Liao teach the method of claim 5, wherein forming the dielectric layer comprises:
conformally depositing a dielectric material (605-1, 2 fig 2) [Xie, 0051/0052] on the front side of the semiconductive layer (see fig 6A) and the gate strip (405-1,405-2, 405-3); and
removing the dielectric material (see fig 11A) on a second side (right side) of the gate strip ( fig 11) opposite to the first side (left side), while remaining the dielectric material on the first side (left side fig 11) of the gate strip remains there on to form the dielectric layer (605-1, 2, fig 11A) [Xie,0047].
Re claim 7 Xie in view of Liao teach the method of claim 1, comprising: forming a silicide layer (a backside contact1105 includes a silicide liner,-not shown) on the back side of the semiconductive layer (see annotated fig above) [Xie, 0061].
Re claim 9 Xie in view of Liao teach the method of claim 1, wherein the dopant is an n-type dopant, and the source/drain structures are n-type source/drain structures. (Liao, 0020)
Re claim 10 Xie in view of Liao teach the method of claim 1, wherein the dopant is a p-type dopant, and the source/drain structures are p-type source/drain structures. (Liao, 0020).
Re claim 11 Xie teach, a method, comprising:
forming a plurality of nanostructures (nanosheet stack 305 , fig 3A/4/5) [0043] arranged in a vertical direction (front side direction fig 4) on a semiconductor strip (semiconductor strip, fig 4) [0049] on a front side of a substrate (100, fig 3A/4) [0049];
forming a functional gate pattern (dummy gates 405-1, 405-2, 405-3, fig 4A/5)[0047]) across at least one of the nanostructures (nanosheet stack 305, fig 3A, 4A, 5) from a top view (see, fig 3A/4A, 5);
growing epitaxial patterns (source/drain regions 620-1, 620-2, fig 5) [0051], S/D regions are epitaxial (0066)] on opposite sides of at least one of the nanostructures (nanosheet stack 305, fig 5).
performing a planarization process (fig 8A) [0061] on a back side of the substrate (substrate 100, fig 8A) to expose the semiconductor strip (semiconductor strip as shown in fig 5, fig 8A) [0061] (substrate 100 is thinned until the bottom surface 815);
forming a power supply voltage line (buried power rail 1125 fig 6) [0067] on a back side of the doped semiconductor strip (see fig 6)
Xie does not teach doping the semiconductive layer with a dopant yielding a doped semiconductive layer, the dopant has a same conductivity type as conductivity type of the source/drain structures.
Liao teaches “forming doped regions (n-type region and P-type, fig 19A) [0020] on the semiconductor layer (50, fig 19) [0020] with a dopant [0020]; n-type or p-type, the dopant (p-type or n-type) has a same conductivity type as the source/drain structures (“ the n-type region 50N can be for forming n-type devices such as NMOS transistors, and the p-type region 50P can be for forming p-type devices such as PMOS transistor “) [0020], and because n-type devices and p-type devices comprises with n-type and p-type source/drain regions, respectively, the dopants in the doped regions have the same conductivity type as the source/drain structures) and forming a power supply voltage line (144/144P, fig 20) [0091] on a back side of the doped semiconductive layer (50, fig 19/20) [0014].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught Liao into the structure Xie of to include doping the semiconductive layer with a dopant yielding a doped semiconductive layer, the dopant has a same conductivity type as conductivity type of the source/drain structures and forming a power supply voltage line on a back side of the doped semiconductive layer as claimed.
The ordinary artisan would have been motivated to modify Xie based on the teaching of Liao in the above manner for the purpose of building circuit incorporating both transistors in a compact form.
Re claim 12 Xie in view of Liao teach the method of claim 11, comprising : forming a metal silicide (a backside contact1105 includes a silicide liner,-not shown) on the backside of the doped semiconductor strip (see annotated fig. above) [Xie, 0066]
Re claim 13 Xie in view of Liao teach the method of claim 11 comprising : forming a leakage barrier (605-1, 605-2 fig 11) [0051] sandwiched between the semiconductor strip (and one of the epitaxial patterns (620-1, 620-2, fig 6A).
Claims 2, 3 and 8 is rejected under 35 U.S.C. 103 as being unpatentable over Xie modified by Liao as applied to claims 1 above and further in view of Yeh et al (US 20230069501A1).
Re claim 2 Xie and Liao do not teach the method of claim 1, wherein doping the semiconductive layer is performed from the back side of the semiconductive layer after forming the source/drain structures.
Yeh teaches doping the semiconductive layer is performed from the back side of the semiconductive layer after forming the source/drain structures (260. (fig 9F1-3) [0068]. (ion implantation process 296 to the semiconductor layer 204 to form 207)[0068].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yeh into the structure of Xie and Liao to include doping the semiconductive layer is performed from the back side of the semiconductive layer after forming the source/drain structures as claimed.
The ordinary artisan would have been motivated to modify Xie based on the teaching of Yeh in the above manner for the purpose of improving operational speed of the device.
Re claim 3 Xie and Liao teach the method of claim 1,
Xie and Liao do not teach doping the semiconductive layer is performed from the front side of the semiconductive layer prior to forming the semiconductor sheets.
Yeh teaches, doping the semiconductive layer (204, fig 3B) [0025] is performed from the front side of the semiconductive layer (204, fig 3B) prior to forming the semiconductor sheets (201, fig 2A- 3D).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Yeh into the structure of Xie and Liao to include doping the semiconductive layer is performed from the front side of the semiconductive layer prior to forming the semiconductor sheets as claimed.
The ordinary artisan would have been motivated to modify Xie and Liao based on the teaching of Yeh in the above manner for the purpose of improving the operational speed of the device.
Re claim 8 Xie teaches the method of claim 1,
Xie does not tech comprising: after doping the semiconductive layer, performing an annealing process on the semiconductive layer.
Yeh does teach after doping the semiconductive layer (207, fig 1B-1C) [0020] , performing an annealing process [0044] on the semiconductive layer.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught into the structure of Yeh to include comprising: after doping the semiconductive layer, performing an annealing process on the semiconductive layer as claimed.
The ordinary artisan would have been motivated to modify Yeh based on the teaching of Xie in the above manner for the purpose of improving material’s structural ad electrical properties.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Xie modified by Liao as applied to claim 11 above and further in view of “Xie 2” (US 20230197503A1).
Re claim 14 Xie in view of Liao teach the method of claim 11,
Xie and Liao do not teach forming a dummy gate pattern extending in parallel with a lengthwise direction of the functional gate pattern from the top view,
wherein the dummy gate pattern has a back-side portion interrupting the semiconductor strip from a cross-sectional view.
Xie 2 teaches, forming a dummy gate pattern ( diffusion break 110, fig 1 and 3-4) [0011] extending in parallel with a lengthwise direction of the functional gate ( gates 140, fig 1) pattern from the top view [0015], wherein the dummy gate pattern having a back-side portion ( the bottom of the diffusion break 110, fig 1) interrupting the semiconductor strip (top portion of substrate 100, fig 1) [0017] from a cross-sectional view. (the diffusion break 110 extends into a substrate 100).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Xie 2 into the structure of Xie and Liao to include forming a dummy gate pattern extending in parallel with a lengthwise direction of the functional gate pattern from the top view, wherein the dummy gate pattern has a back-side portion interrupting the semiconductor strip from a cross-sectional view as claimed.
The ordinary artisan would have been motivated to modify Xie and Liao based on the teaching of Xie 2 in the above manner for the purpose of providing the benefit of electrically isolating transistors in different areas of the device.
Re claim 15 Xie and Liao do not teach the method of claim 11, further comprising:
Xie and Liao do not teach forming a dummy gate pattern extending in parallel with a lengthwise direction of the functional gate pattern from the top view, wherein the dummy gate pattern has a back-side portion inlaid in the semiconductor strip from a cross-sectional view.
Xie 2 teaches a dummy gate pattern (diffusion break 110, fig 1)extending in parallel with a lengthwise direction of the gate structure (gates 140, fig 1) [0015] “The diffusion break 110 is formed between two S/D regions 130, one in the active region 105A and one in the active region 105B” meaning that diffusion break extends parallel to the gate pattern from top view”, the dummy gate structure (diffusion break 110, fig 1) having a back-side (the bottom of diffusion break 110, fig 1) inlaid in the silicon layer ( top portion of substrate 100, fig 1) [0017] the diffusion break 110 extends into a substrate 100”) from a cross sectional view (fig 1 shows a cross sectional view).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Xie 2 into the structure Xie and Liao of to include forming a dummy gate pattern extending in parallel with a lengthwise direction of the functional gate pattern from the top view, wherein the dummy gate pattern has a back-side portion inlaid in the semiconductor strip from a cross-sectional view as claimed.
The ordinary artisan would have been motivated to modify Xie and Liao based on the teaching Xie 2 in the above manner for the purpose of providing the benefit of electrically isolating transistors in different areas of the device.
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al (US20230093101A1) in view of Xie 3 (US 20230197503A1) and Liao et al (US 20210336063A1).
Re claim 21. Xie teaches a method, comprising:
forming a first stack of nanostructures (left stack fig 5A) [0040], a second stack of nanostructures (middle stack, fig 5A) [0040], and a third stack of nanostructures (right stack fig 5A) [0040] over a semiconductor layer (see fig above, top of the substrate) [0061], the second stack positioned between the first stack and the third stack (fig 5A);
forming an isolation structure adjacent the semiconductor layer (fins and shallow trench isolations (STI) are formed between the neighboring nanosheet fins (not shown in X-cut see fig 5A) [0046];
forming a source/drain region (source/drain regions 620-1, fig 6A) [0051] between the first stack(left stack, fig 6A) and the second stack (middle stack, fig 6A);
removing portions of the nanostructures of the second stack (middle stack, fig 5A/5B) yielding an opening (501-1, fig 5B) [0049] extending into the semiconductor layer (top of substrate) [0061], the opening further extending into the isolation structure (STI);
Xie does not teach forming a dielectric gate in the opening.
Xie 3 does teach forming a dielectric gate (110, fig 2E) [0011] in the opening (235, fig 2E) [0025].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Xie 3 into the structure of Xie to include forming a dielectric gate in the opening as claimed.
The ordinary artisan would have been motivated to modify Xie 3 based on the teaching of Xie in the above manner for the purpose of electrically isolate the components.
Xie and Xie 3 do not teach doping the semiconductor layer yielding a doped semiconductor layer having same type conductivity type as a conductivity of source /drain region.
Liao does teach “forming doped regions (n-type region and P-type, fig 19A) [0020] on the semiconductor layer (50, fig 19) [0020] with a dopant [0020]; n-type or p-type, the dopant (p-type or n-type) has a same conductivity type as the source/drain structures (“the n-type region 50N can be for forming n-type devices such as NMOS transistors, and the p-type region 50P can be for forming p-type devices such as PMOS transistor “) [0020], and because n-type devices and p-type devices comprises with n-type and p-type source/drain regions, respectively, the dopants in the doped regions have the same conductivity type as the source /drain region).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught Liao into the structure of Xie and Xie 3 to include doping the semiconductive layer with a dopant yielding a doped semiconductive layer, having a same conductivity type as conductivity type of the source/drain region as claimed.
The ordinary artisan would have been motivated to modify Xie and Xie 3 based on the teaching of Liao in the above manner for the purpose of building circuit incorporating both transistors in a compact form.
Re claim 22 Xie in view of Xie 3and Liao teach forming a conductive line (1105/ 1115, fig. 11A) [Xie, 0066] under the doped semiconductor layer (top of substrate 100, fig 8A) [Xie, 0061].
Re claim 23 Xie in view of Xie 503 and Liao teach the method of claim 22, comprising: prior to forming the conductive line (1105, fig 11A) [Xie, 0066], forming a silicide layer (not shown) under the doped semiconductor layer, the conductive line being formed over the silicide layer (backside contact includes a silicide liner- not shown) [0066].
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Xie modified by Xie 3 and Liao as applied to claim 21 above and further in view of Jiang et al (US 9502265 B1).
Re claim 24 Xie in view of Xie 503 and Liao teach the method of claim 23,
Xie, Xie 503 and Liao do not teach wherein forming the silicide layer comprises: forming the silicide layer having an upper surface contiguous with a bottom surface of the dielectric gate.
Jiang does teach forming the silicide layer (214, fig 25) [para 21] comprises: forming the silicide layer (214) having an upper surface contiguous with a bottom surface of the dielectric gate (240, fig 25) [Para 47].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Jiang into the structure of Xie, Xie503 and Lia0 to forming the silicide layer comprises: forming the silicide layer having an upper surface contiguous with a bottom surface of the dielectric gate include as claimed.
The ordinary artisan would have been motivated to modify Xie, Xie3 and Liao based on the teaching of Jiang in the above manner for the purpose of improving device performance.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Xie modified by Xie 3 and Liao as applied to claim 21 and further in view of Liaw et al (US 9805985B2).
Re claim 25 Xie in view of Xie 503 and Liao teach the method of claim 21,
Xie, Xie 503 and Liao do not teach forming the dielectric gate comprises: forming the dielectric gate to extend partially into the isolation structure.
Liaw does teach forming the dielectric gate comprises: forming the dielectric gate ( 124, fig 6F) [col 10 lines 17-21] to extend partially into the isolation structure (col 15 lines 2-5].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Liaw into the structure of Xie, Xie 3 and Liao to include forming the dielectric gate comprises: forming the dielectric gate to extend partially into the isolation structure as claimed.
The ordinary artisan would have been motivated to modify Xie, Xie 3 and Liao based on the teaching of Liaw in the above manner for the purpose of to reduce parasitic capacitance [col 10, lines 15-20].
Conclusion
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/PRATIKSHA JAYANT LOHAKARE/Examiner, Art Unit 2818
/CALEB E HENRY/Primary Examiner, Art Unit 2818