Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/193197 filed on 03/30/23.
Claims 1-20 are remain pending in the application.
Oath/Declaration
The oath/declaration filed on March 30th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jadhav et al. (U.S. Pub. 20220399881).
As to claims 1 the prior art teaches a method, comprising:
determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design (see fig 7 element 714 paragraph 0083);
and performing, using the computer hardware, control set optimization on the circuit design by: performing a clock-enable-only control set reduction for each super control set, and performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set (see fig 2, 4 paragraph 0029-0032);
and selectively modifying the circuit design by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set (see fig 2, 4 paragraph 0031-0034).
As to claims 2, 9 and 16 the prior art teaches wherein the performing control set optimization is performed prior to floor-planning the circuit design (see fig 7 element 714 paragraph 0085-0088).
As to claims 3, 10 and 17, the prior art teaches further comprising:
allocating flip-flops of the circuit design to a specified number of groups prior to the determining the control sets (see fig 1-2 paragraph 0029-0031);
wherein the determining the regular control sets, the super control sets, and the mega control sets is performed on a per-group basis (see fig 2-3 paragraph 0030-0034);
and the performing control set optimization on the circuit design is performed on a per-group basis (see fig 2-4 paragraph 0050-0055).
As to claim 4, 11 and 18, the prior art teaches further comprising:
floor-planning the circuit design (see fig 7 element 722 paragraph 0086);
and performing the control set optimization on the circuit design again subsequent to the floor-planning (see fig 7 element 718 paragraph 0083-0085)
As to claim 5, 12 and 19, the prior art teaches wherein the control set optimization, as performed on the circuit design subsequent to the floor-planning, is performed for each of a plurality of locations of a window moved across a target integrated circuit for the circuit design (see fig 7 paragraph 0085-0089).
As to claim 6, 13 and 20, the prior art teaches wherein: for a selected super control set, processing fewer than all flip-flops of the selected super control set during the clock-enable-only control set reduction (see fig, 3-4, 7 paragraph 0052-0055);
and for a selected mega control set including a plurality of subgroups, performing the set/reset control set reduction and the clock-enable control set reduction for fewer than all subgroups of the plurality of subgroups (see fig 3-4, 7 paragraph 0055-0059).
As to claim 7 and 14 the prior art teaches wherein non-reducible flip-flops of the circuit design are excluded from the control set reductions (see fig 1-2 paragraph 0023-0025).
As to claim 8, the prior art teaches a system, comprising:
one or more hardware processors configured to initiate operations including: determining regular control sets, super control sets, and mega control sets for a circuit design (see fig 7 element 714 paragraph 0083);
and performing control set optimization on the circuit design by: performing a clock-enable-only control set reduction for each super control set, and performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set (see fig 2, 4 paragraph 0029-0032);
and selectively modifying the circuit design by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set (see fig 2, 4 paragraph 0031-0034).
As to claim 15 the prior art teaches a computer program product comprising one or more computer readable storage mediums having program instructions embodied therewith, wherein the program instructions are executable by computer hardware to cause the computer hardware to initiate executable operations comprising:
determining regular control sets, super control sets, and mega control sets for a circuit design (see fig 7 element 714 paragraph 0083);
and performing control set optimization on the circuit design by: performing a clock-enable-only control set reduction for each super control set, and performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set (see fig 2, 4 paragraph 0029-0032);
and selectively modifying the circuit design by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set (see fig 2, 4 paragraph 0031-0034).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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