DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
Applicant’s response, dated 12/16/2025, to a non-final Office Action, dated 09/17/2025 is acknowledged. Claims 1-9 and 12-20 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-11, 13-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner et. al., U.S. Pat. Pub. 2006/0087031, hereafter Gardner, in view of Iwata et. al., U.S. Pat. 5,512,712, hereafter Iwata.
Regarding claim 1, Gardner discloses (Figs 4-6) a component carrier (PCB, Fig. 3, unlabeled bottom layer in Fig. 6), comprising:
a stack comprising at least one electrically conductive layer structure [27],[29] and at least one electrically insulating layer structure (bottom layer below [27], which is a solder mask of PCB);
a solder mask [28] (par. [0032]) arranged at least on part of an exterior surface of the stack, said solder mask being patterned for defining curved sidewalls (of the openings [31], see Fig. 6); and
a legend marking [30] on and/or above the stack, in direct physical contact with the solder mask and at least partially interacting with the curved sidewalls (see Figs 4-6).
Gardner fails to explicitly disclose
wherein the legend marking has curved sidewalls, and wherein the curved sidewalls of the legend marking are in direct physical contact with the curved sidewalls of the solder mask, or
wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask merge with a beak shape, and wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask approach until they meet each other in a common point or line.
However, Iwata discloses (Fig. 4)
wherein the legend marking [40a] has curved sidewalls, and wherein the curved sidewalls of the legend marking are in direct physical contact with the curved sidewalls of the solder mask [30], (or
wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask merge with a beak shape), and wherein the curved sidewalls of the legend marking [40a] and the curved sidewalls of the solder mask [30] approach until they meet each other in a common point or line (see Fig. 4).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the legend mark of Gardner with the teachings of alignment mark of Iwata, because Iwata teaches (abstract) that such marks are highly visible and well protected. It would have been obvious to one of ordinary skill in the art to apply alignment mark structure to legend marking of Gardner because these marks are similar in scope and purpose.
Regarding claim 2, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Figs 5,6) wherein the legend marking [30] is arranged to be visible from a top side of the component carrier (PCB).
Regarding claim 4, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Figs 5,6, par. [0032]) wherein the legend marking [30] comprises a dielectric ink or a dielectric film.
Regarding claim 5, Gardner in view of Iwata discloses everything as applied above.
Iwata discloses (Figs 1, 2) in a different embodiment wherein at least part of the legend marking [40] is embedded in the solder mask [30].
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to use embedded legend marking of Iwata in the invention of Gardner in view of Iwata because such labels are commonly used on printed circuit boards and are a part of commercially available software for the design of custom labels. A legend marking is always a part of a printed circuit board.
Regarding claim 6, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Figs 5,6, see Fig. 6)) wherein an outermost exterior surface of the legend marking [30] is retracted with respect to an outermost exterior surface of the solder mask [28].
Regarding claim 7, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Figs 5, 6) wherein at least part of the solder mask [28] is formed on the legend marking [30] (in the broadest reasonable interpretation, the claim does not require the solder mask to be formed on top of the legend marking, it can be formed on a side, as is the case for Fig. 6 of Gardner).
Regarding claim 8, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Figs 5,6) wherein at least part of the legend marking [30] is formed directly on at least part of the at least one electrically conductive layer structure [27], [29].
Regarding claim 9, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Fig. 6) wherein the patterned solder mask [28] has convex sidewalls.
Regarding claim 13, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (par. [0027]) wherein the solder mask and the legend marking comprise materials having different color.
Regarding claim 14, Gardner in view of Iwata discloses everything as applied above. Gardner fails to explicitly disclose wherein a part of the legend marking arranged between a part of the solder mask and another part of the solder mask is formed with an undercut.
However, the curved sidewall of the solder mask is very close to having an undercut, see Fig. 6.
Therefore, having an undercut involves only a small modification of the shape of the sidewall of Gardner. In addition, space occupied by the electrode [27] in Fig. 6 is a space missing from solder resist [28] and can be considered to be an undercut.
A modification of shape is normally considered to be obvious to one having ordinary skill in the art, especially a small modification of shape that will turn the sidewall of Gardner into one with an undercut. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (MPEP, Latest Edition, 2144.04.IV.B).
Regarding claim 15, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Fig. 6) wherein the at least one electrically conductive layer structure [27],[29] is in direct physical contact with the solder mask [28] and the legend marking [30].
Regarding claim 16, Gardner in view of Iwata discloses everything as applied above.
Iwata further discloses (Fig. 3) wherein at least one component [50], being surface mounted above the stack or embedded in the stack, is in direct physical contact with the solder mask [30] and/or the legend marking.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to include a surface mounted component because Iwata teaches (Col. 6, lines 44-48) that there will not be any necessity to disadvantageously increase the amount of solder material for connecting the external terminals of the device and the connector sections, or to extend the external terminals of the electronic device disadvantageously to reach the connector sections.
Regarding claim 18, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Fig. 6) wherein a transition region between said solder mask [28] and said legend marking [30] defines a non-planar, for example angled, exterior surface portion of the component carrier (The walls of [28] are curved).
Regarding claim 19, Gardner discloses a method of manufacturing a component carrier, wherein the method comprises (Figs 5,6):
providing a stack comprising at least one electrically conductive layer structure [27], [29] and at least one electrically insulating layer structure (bottom layer below [27], which is a solder resist of PCB;
forming a solder mask [28] at least on part of an exterior surface of the stack, said solder mask being patterned for defining curved sidewalls; and
forming a legend marking [30] on and/or above the stack, in direct physical contact with the solder mask [28] and at least partially interacting with the curved sidewalls.
Gardner fails to explicitly disclose
wherein the legend marking has curved sidewalls, and wherein the curved sidewalls of the legend marking are in direct physical contact with the curved sidewalls of the solder mask, or
wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask merge with a beak shape, and wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask approach until they meet each other in a common point or line.
However, Iwata discloses (Fig. 4)
wherein the legend marking [40a] has curved sidewalls, and wherein the curved sidewalls of the legend marking are in direct physical contact with the curved sidewalls of the solder mask [30], (or
wherein the curved sidewalls of the legend marking and the curved sidewalls of the solder mask merge with a beak shape), and wherein the curved sidewalls of the legend marking [40a] and the curved sidewalls of the solder mask [30] approach until they meet each other in a common point or line (see Fig. 4).
It would have been obvious to one of ordinary skill in the art prior to effective filing date of the instant application to modify the legend mark of Gardner with the teachings of alignment mark of Iwata, because Iwata teaches (abstract) that such marks are highly visible and well protected. It would have been obvious to one of ordinary skill in the art to apply alignment mark structure to legend marking of Gardner because these marks are similar in scope and purpose.
Regarding claim 20, Gardner in view of Iwata discloses everything as applied above. Gardner further discloses (Fig. 6) wherein the method comprises forming the legend marking [30] after forming the solder mask [28] (this order of steps is implicit).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gardner et. al., U.S. Pat. Pub. 2006/0087031, hereafter Gardner, in view of Iwata et. al., U.S. Pat. 5,512,712, hereafter Iwata, and further in view of Hahn et. al., U.S. Pat. Pub. 2020/0396845, hereafter Hahn.
Regarding claim 3, Gardner in view of Iwata discloses everything as applied above. Gardner in view of Iwata fails to explicitly disclose wherein the legend marking comprises an alphanumerical code, a location indicator, a QR code, a barcode, a logo and/or an icon.
However, Hahn discloses (par. [0016]) wherein the legend marking comprises an alphanumerical code, a location indicator, a QR code, a barcode, a logo and/or an icon.
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to use the legend marking of Hahn in the invention of Gardner because such labels are commonly used on printed circuit boards and are a part of commercially available software for the design of custom labels. A legend marking is always a part of a printed circuit board.
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gardner et. al., U.S. Pat. Pub. 2006/0087031, hereafter Gardner, in view of Iwata et. al., U.S. Pat. 5,512,712, hereafter Iwata, and further in view of JP2011-119522, hereafter ‘522 (of record, the Examiner attaches machine translation).
Regarding claim 12, Gardner in view of Iwata discloses everything as applied above. Gardner in view of Iwata fails to explicitly disclose wherein an exterior surface of a section of the patterned solder mask between curved sidewalls has a profile comprising at least one local protrusion.
However, ‘522 discloses (Fig. 7B) wherein an exterior surface of a section of the patterned solder mask [13] between curved sidewalls has a profile comprising at least one local protrusion (forming “E”).
It would have been obvious to one having ordinary skill in the art prior to effective filing date of the instant application to modify Gardner to form a letter by protrusions as taught by ‘522, because such characters are easier to read.
Regarding claim 17, Gardner in view of Iwata discloses everything as applied above. Gardner in view of Iwata fails to explicitly disclose wherein the patterned solder mask has a maximum in vertical direction between a respective one of the curved sidewalls and a plateau region.
However, ‘522 discloses (Fig. 7B) wherein the patterned solder mask has a maximum in vertical direction between a respective one of the curved sidewalls (outside “E” letter) and a plateau region (Insider “E” letter).
It would have been obvious one having ordinary skill in the art prior to effective filing date of the instant application to modify Gardner to form a letter by protrusions as taught by ‘522, because such characters are easier to read.
Response to Arguments
Applicant’s arguments with respect to claims 1-9, 12-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR V BARZYKIN whose telephone number is (571)272-0508. The examiner can normally be reached Monday-Friday, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/VICTOR V BARZYKIN/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893