DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-8) in the reply filed on 12/16/2025 is acknowledged. In this reply, Applicant also added new claims 21-32, which depend from claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, 4, 6-8, 21, 23-26, 29, 30, 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2003/0011075 (Ohuchi) in view of U.S. Patent Application Publication No. 2010/0258925 (Jeon).
Ohuchi discloses (at least Figs. 1 and 4)
1. (Currently Amended) A packaging substrate comprising a plurality of packaging units, each packaging unit being defined by a closed packaging line, wherein the packaging substrate comprises:
a base substrate 1 / 11 having a first surface (bottom) and a second surface (top) that are opposite to each other;
a plurality of pads 24 provided on the first surface (bottom) of the base substrate 1 /11; and
a metal layer 22 provided on the second surface (top) of the base substrate 1 / 11;
wherein in one packaging unit 2, the metal layer 21 / 22 comprises a plurality of lead pads 22, at least one lead pad 22 extends from an inner side of the one packaging unit 2 defined by the closed packaging line 40b to an outer side of the one packaging unit 2, the lead pad 22 is connected to one solder pad 24 by means of a connecting member (in via hole 3) penetrating through the base substrate 1 / 11.
Ohuchi fails to disclose
a plurality of solder pads; and
and an orthographic projection of the connecting member on the base substrate at least partially covers the closed packaging line.
Jeon teaches (at least Figs. 6A-6I)
A packaging substrate comprising a plurality of packaging units, each packaging unit being defined by a closed packaging line, wherein the packaging substrate comprises:
a plurality of solder pads 200(b); and
and an orthographic projection of the connecting member (side surface of 200(b), see [0162] which is similar to 104(b) that extends through the substrate 100) on the base substrate 204 at least partially covers the closed packaging line (border between packaging units 246).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a plurality of solder pads and a connecting member having an orthographic projection. The motivation would be to provide for a conductive and/or thermal path for a semiconductor die through the substrate and to an underlying circuit board, to provide a more compact package, and to increase the lead count as taught by Jeon ([0167], [0168], [0253]).
Ohuchi discloses
3. (Currently Amended) The packaging substrate of claim 1, wherein the metal layer 21 / 22 further comprises at least one carrier portion 22, the carrier portion 22 being used for carrying at least one chip 20.
Jeon teaches
4. (Original) A grid array package having a body, and characterized in that the grid array package comprises:
a packaging unit 246 obtained by cutting the packaging substrate (see MPEP 2113, product-by-process language is not being given patentable weight) of claim 1, and at least one chip 226 provided on the metal layer (portion of 200(b) attached to adhesive 218) of the packaging unit 246;
wherein the body of the grid array package has at least one third surface (side) perpendicular to the first surface (bottom), and the plurality of solder pads 200(b) are provided at an edge of the first surface (bottom) and extend from the first surface (bottom) to the third surface (side).
Ohuchi discloses
6. (Currently Amended) The grid array package of claim 4, wherein the metal layer 21 /22 comprises at least one carrier portion 22, and the at least one chip 20 is provided on the carrier portion 22.
Ohuchi discloses
7. (Currently Amended) The grid array package of claim 4, wherein the chip 20 is connected to a lead pad (portion connected to electrode 20a) of the metal layer 21 / 22 by means of a lead 23.
Ohuchi discloses
8. (Currently Amended) The grid array package of claim 7,
Ohuchi appears to disclose the below three elements are integrally formed and therefore made of the same material
21. (New) The packaging substrate of claim 1, wherein the connecting member (in via hole 3), the at least one lead pad 22, and the one solder pad 24 are made of a same material.
Ohuchi appears to disclose
23. (New) The packaging substrate of claim 1, wherein each packaging unit 2 includes a plurality of connecting members (in via hole 3), and each of the plurality of connecting members (in via hole 3) and solder pads 24 of one packaging unit 2 are not shared with other packaging units 2.
Ohuchi discloses
24. (New) The packaging substrate of claim 1, wherein the connecting member (in via hole 3) is a through hole extending between the first surface (bottom) and second surface (top) of the base substrate 1 /11.
Ohuchi discloses
25. (New) The packaging substrate of claim 1,
Ohuchi discloses
26. (New) The packaging substrate of claim 1,
Ohuchi discloses
29. (New) The packaging substrate of claim 1, wherein the closed packaging line is formed by a groove 25b or a score line on the base substrate.
Ohuchi discloses
30. (New) The packaging substrate of claim 1, wherein the at least one lead pad 22 extends to a side edge of each packaging unit 2.
Ohuchi discloses
32. (New) The packaging substrate of claim 1, wherein the connecting member (in via hole 3) is formed integrally with the one solder pad 24.
Claim(s) 2, 5, 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohuchi in view of Jeon as applied to claims 1, 4 above, and further in view of U.S. Patent Application Publication No. 2008/0217758 (Liao).
The combination of references fails to teach
2. (Currently Amended) The packaging substrate of claim 1, wherein the packaging substrate further comprises a solder mask, the solder mask being provided on the first surface of the base substrate and exposing each solder pad.
Liao teaches (at least Fig. 1B)
A packaging substrate comprising:
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a solder mask in the modified substrate of Ohuchi. The motivation would be a solder mask is well-known in the packing art as discussed in Liao. (See MPEP 2144.03)
Liao teaches
5. (Currently Amended) The grid array package of claim 4,
Liao teaches
27. (New) The packaging substrate of claim 1, wherein the solder pads 154 each have a gold-plated surface layer ([0037]).
Claim(s) 22, 28, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohuchi in view of Jeon as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2019/0318984 (Kim).
The combination of references fails to teach
22. (New) The packaging substrate of claim 1, wherein the plurality of solder pads are arranged in a staggered configuration on the first surface of the base substrate.
Kim teaches (at least Figs. 2b, 2c, 10a)
A packaging substrate comprising:
wherein the plurality of solder pads 128 are arranged in a staggered configuration on the first surface (bottom) of the base substrate 190.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a staggered configuration in the modified substrate of Ohuchi. The motivation would be to provide enhanced contact surface area along the side surface post singulation, given variance during cutting along dicing lines as taught by Kim ([0034]).
Kim teaches determining the number of solder pads is based on the desired surface area
28. (New) The packaging substrate of claim 1, wherein each packaging unit comprises nine solder pads, with five solder pads in an upper row and four solder pads in a lower row.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a certain number of solder pads on opposite rows in the modified substrate of Ohuchi. The motivation would be based on optimization and routine engineering design considerations as discussed in Kim. (See MPEP 2144.05)
Kim teaches (Fig. 3c and Fig. 10a)
31. (New) The packaging substrate of claim 1, wherein the lead pads 128 (top) corresponding to the solder pads 128 (bottom) are arranged in a staggered configuration.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2007/0018287 (Coenen), 2007/0138611 (Barbee), 2008/0102563 (Lange), 2009/0294978 (Ota), 2010/0258925 (Jeon), 2023/0098907 (Li), 2023/0317567 (Huang), U.S. Patent No. 8,017,447 (Olsen) teach a packaging substrate having solder pads, lead pads, a metal layer, and a connecting member.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893