Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-20 in the reply filed on 12/30/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jang et al., US 2022/0199670.
Regarding claim 1, Jang discloses (3C and related text) a method for forming an integrated circuit (IC), the method comprising: forming a plurality of photodetectors (PD, image sensor) within a first substrate (100); forming a first interconnect structure (330) on a front side (100b) of the first substrate (100); forming a first bond structure on the first interconnect structure (330), wherein the first bond structure comprises a first plurality of conductive bond pads (61/62) and a first plurality of shield structures (71/72) disposed between adjacent conductive bond pads (61/62) among the first plurality of conductive bond pads (71/72); forming a second interconnect structure (410) on a front side of a second substrate (400); forming a second bond structure on the second interconnect structure, wherein the second bond structure comprises a second plurality of conductive bond pads (81/82) and a second plurality of shield structures (91/92) disposed between adjacent conductive bond pads (81/82) in the second plurality of conductive bond pads, and wherein a layout of the second bond structure is symmetrical with a layout of the first bond structure (fig. 3C); and bonding the first bond structure to the second bond structure at a first bond interface (fig. 3C).
Allowable Subject Matter
Claims 17-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 25-35 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or suggest, singularly or in combination at least the limitation “performing a first etch process on the dielectric structure to form a first plurality of openings and a second plurality of openings in the dielectric structure; forming a first plurality of conductive bond pads in the first plurality of openings; and forming a first plurality of shield structures in the second plurality of openings, wherein the first plurality of shield structures are interposed between neighboring conductive bond pads of the first plurality of conductive bond pads, wherein a first shield structure of the first plurality of shield structures is between a first pair of conductive bond pads of the first plurality of conductive bond pads and has a length greater than a distance between the first pair of conductive bond pads; forming a second plurality of semiconductor devices on a first surface of a second substrate; forming a second bond structure on the first surface of the second substrate; and bonding the first substrate to the second substrate, wherein a bond interface is between the first bond structure and the second bond structure” is the first major difference between the prior art and the claimed invention and the second major difference is the limitation “the first conductive bond pad is electrically coupled to the first floating diffusion node and the second floating diffusion node, and wherein the first conductive bond pad is spaced between a pair of neighboring shield structures of the first plurality of shield structures; forming a second bond structure on a second substrate of a second IC chip, wherein the second bond structure comprises a second plurality of conductive bond pads and a second plurality of shield structures in a second bond dielectric; and bonding the first IC chip to the second IC chip at a bond interface, wherein the first plurality of conductive bond pads and the first plurality of shield structures are bonded, respectively, to the second plurality of conductive bond pads and the second plurality of shield structures at the bond interface” as recited in claim 31.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL A GEBREMARIAM whose telephone number is (571)272-1653. The examiner can normally be reached 8:30-4PM.
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/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811