DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/19/26 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 21-26, 28-34 have been considered but are moot because the new ground of rejection relies on new references for teaching matters specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 21, 22, 28, 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2009/0170241 (Shim) in view of U.S. Patent Application Publication No. 2013/0037927 (Rogren).
Shim discloses
1. (Currently Amended) A method of forming a semiconductor package comprising:
coupling a plurality of die 90, 98 (36, 40) directly over and to a plurality of pre-plated pads 94 (34) of a pre-plated pad carrier 30, the pre-plated pad carrier 30 comprising a metal carrier ([0026], [0027], [0036]) coupled to the plurality of pre-plated pads 94;
wire bonding 96, 100 the plurality of die 90, 98 to the plurality of pre-plated pads 94;
applying a mold compound 101 over the plurality of die 90, 98;
removing the metal carrier 30 ([0036]); and
singulating a plurality of semiconductor packages after the metal carrier is removed ([0003], [0023], [0036]).
Shim fails to disclose
wherein each pre-plated pad of the plurality of pre-plated pads comprises a solderable layer coupled between the metal carrier and a wire bondable layer.
Rogren teaches
A method comprising:
wherein each pre-plated pad of the plurality of pre-plated pads 140 comprises a solderable layer 143 coupled between the metal carrier 120 (conventional temporary support member is removed and a plurality of packages are provided after singulation, [0096]) and a wire bondable layer 147 (Figs. 11-13, 19, 20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a solderable layer and a wire bondable layer in Shim. The motivation would be to provide corrosion resistance and compatibility with thermosonic bonding, thereby providing plated pads as taught by Rogren ([0028]).
Shim discloses
21. (Currently Amended) A method of forming a semiconductor package comprising:
coupling a plurality of die 90, 98 (36, 40) directly over and to a plurality of pre-plated pads 94 (34) of a pre-plated pad carrier 30, the pre-plated pad carrier 30 comprising a metal carrier ([0026], [0027], [0036]) coupled to the plurality of pre-plated pads 94;
wire bonding 96, 100 the plurality of die 90, 98 to the plurality of pre-plated pads 94;
applying a mold compound 101 over the plurality of die 90, 98;
removing the metal carrier 30 ([0036]); and
singulating a plurality of semiconductor packages ([0003], [0023], [0036]);
wherein each die of the plurality of die 90, 98 (36, 40) is directly coupled over and to two pre-plated pads (solder bumps 38, 42 and die 80, 84 mounted to pads 78 by bumps 82, 86, [0027], [0034]) of the plurality of pre-plated pads 94 (34).
Shim fails to disclose
wherein each pre-plated pad of the plurality of pre-plated pads comprises a solderable layer coupled between the metal carrier and a wire bondable layer.
Rogren teaches
A method comprising:
wherein each pre-plated pad of the plurality of pre-plated pads 140 comprises a solderable layer 143 coupled between the metal carrier 120 (conventional temporary support member is removed and a plurality of packages are provided after singulation, [0096]) and a wire bondable layer 147 (Figs. 11-13, 19, 20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a solderable layer and a wire bondable layer in Shim. The motivation would be to provide corrosion resistance and compatibility with thermosonic bonding, thereby providing plated pads as taught by Rogren ([0028]).
The combination of references teaches
22. (Currently Amended) The method of claim 21, wherein wire bonding 96, 100 the plurality of die 90, 98 to the plurality of pre-plated pads 94 comprises wire bonding 96, 100 the plurality of die 90, 98 to the plurality of pre-plated pads 94 directly under the plurality of die 90, 98.
Shim discloses
28. (Currently Amended) A method of forming a semiconductor package comprising:
coupling a plurality of die 90, 98 (36, 40) directly over and to a plurality of pre-plated pads 94 (34) of a pre-plated pad carrier 30, the pre-plated pad carrier 30 comprising a metal carrier ([0026], [0027], [0036]) coupled to the plurality of pre-plated pads 94;
wire bonding 96, 100 the plurality of die 90, 98 to the plurality of pre-plated pads 94;
applying a mold compound 101 over the plurality of die 90, 98;
removing the metal carrier 30 ([0036]); and
singulating a plurality of semiconductor packages after the metal carrier is removed ([0003], [0023], [0036]).
Shim fails to disclose
wherein each pre-plated pad of the plurality of pre-plated pads comprises a solderable layer coupled between the metal carrier and a wire bondable layer;
wherein the wire bondable layer overhangs the solderable layer and forms a mold lock.
Rogren teaches
A method comprising:
wherein each pre-plated pad of the plurality of pre-plated pads 140 comprises a solderable layer 143 coupled between the metal carrier 120 (conventional temporary support member is removed and a plurality of packages are provided after singulation, [0096]) and a wire bondable layer 147 (Figs. 11-13, 19, 20);
wherein the wire bondable layer 147 overhangs the solderable layer 143 and forms a mold lock (the pad edges may taper or be stepped in an overhang fashion, thereby permitting mechanical locking of the pad within the mold compound, Figs. 22, 26).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a solderable layer and a wire bondable layer in Shim. The motivation would be to provide corrosion resistance and compatibility with thermosonic bonding, thereby providing plated pads as taught by Rogren ([0028]). Further, mold locking would improve retention of the wire-bonded pad in the mold compound and reduce pad separation from the package ([0019]).
Shim discloses
30. (Currently Amended) The method of claim 28, wherein each die of the plurality of die 90, 98 (36, 40) is directly coupled over and to two pre-plated pads (solder bumps 38, 42 and die 80, 84 mounted to pads 78 by bumps 82, 86, [0027], [0034]) of the plurality of pre-plated pads 94 (34).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2010/0210071 (Mahler) and 2004/0070042 (Lee).
The combination of references fails to teach
2. (Currently Amended) The method of claim 1, wherein each pre-plated pad of the plurality of pre-plated pads further comprises an etch stop layer coupled between the solderable layer and the metal carrier, and wherein the wire bondable layer directly coupled to the solderable layer.
Mahler teaches
A method comprising:
wherein each pre-plated pad of the plurality of pre-plated pads 102d – 102j / 162d – 162j further comprises an etch stop layer ([0058], [0059], [0068], [0069]) coupled to the metal carrier 100 / 160.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an etch stop plating layer in the modified method of Shim. The motivation would be to protect the plated pad during selective etching of the metal carrier, thereby controlling removal of the carrier as taught by Mahler ([0041], [0047], [0057], [0059], [0062], [0067], [0069])
Lee teaches
wherein each pre-plated pad 17 further comprises the solderable layer 40 and the metal carrier 15, and wherein the wire bondable layer 38 directly coupled to the solderable layer 40.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a stacked pad in the modified method of Shim. The motivation would be to provide solder functionality while directly overlying a layer as a surface suitable for wire bonding, thereby providing a plated pad having both functionality as taught by Lee ([0014]-[0017]). Further, reduction in die size is allowed by the placing of bond pads over the active devices. Furthermore, there are no restrictions on underlying interconnect metal routing and the composite pad provides for absorption of force during wire bonding ([0107], [0108]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2009/0102028 (Krishnan), cited by Applicant (D4 in Search Report).
The combination of references fails to teach
3. (Previously Presented) The method of claim 1, wherein a semiconductor package of the plurality of semiconductor packages comprises a multi-chip module package.
Krishnan teaches (Figs. 9, 10)
A method comprising:
wherein the semiconductor package of the plurality of semiconductor packages 102 comprises a multi-chip module package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a multi-chip module package in the modified method of Shim. The motivation would be mere duplication of parts based on engineering design considerations as taught by Krishnan ([0036]-[0041]). See MPEP 2144.04.
Claim(s) 4, 5 is/are rejected under 35 U.S.C. 103 as being obvious over Shim in view of Rogren as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2018/0145013 (Truhitte), cited by Applicant (D1 in Search Report).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The combination of references fails to teach
4. (Currently Amended) The method of claim 1, wherein the plurality of pre-plated pads form a plurality of wettable flanks in each semiconductor package of the plurality of semiconductor packages.
The combination of references fails to teach
5. (Previously Presented) The method of claim 1, wherein a semiconductor package of the plurality of semiconductor packages comprises a chip-on-lead package.
Truhitte teaches
A method comprising:
wherein the plurality of pads 102 / 104 form a plurality of wettable flanks 124 ([0026], [0031]) in each semiconductor package of the plurality of semiconductor packages 122;
wherein a semiconductor package of the plurality of semiconductor packages ([0074]) comprises a chip-on-lead package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in the modified method of Shim. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04. Also, providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Claim(s) 23, 24, 26 is/are rejected under 35 U.S.C. 103 as being obvious over Shim in view of Rogren as applied to claim 21 above, and further in view Truhitte.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The combination of references fails to teach
23. (Previously Presented) The method of claim 21, wherein a semiconductor package of the plurality of semiconductor packages comprises a chip-on-lead package.
The combination of references fails to teach
24. (Currently Amended) The method of claim 21, wherein each pre-plated pad of the plurality of pre-plated pads in each semiconductor package of the plurality of semiconductor packages comprises a wettable flank.
Truhitte teaches
A method comprising:
wherein the plurality of pre-plated pads 102 / 104 form a plurality of wettable flanks 124 ([0026], [0031]) in each semiconductor package of the plurality of semiconductor packages 122;
wherein a semiconductor package of the plurality of semiconductor packages ([0074]) comprises a chip-on-lead package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in the modified method of Shim. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04. Also, providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Rogren teaches (Fig. 6b)
26. (Currently Amended) The method of claim 25, wherein the wire bondable layer 147 overhanging the solderable layer 143 forms a mold lock (the pad edges may taper or be stepped in an overhang fashion, thereby permitting mechanical locking of the pad within the mold compound, Figs. 22, 26).
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren as applied to claim 21 above, and further in view U.S. Patent Application Publication No. 2013/0334674 (Zheng).
Rogren teaches
25. (Currently Amended) The method of claim 21, wherein the wire bondable layer 147 of each pre-plated pad 140 overhangs the solderable layer 143 (the pad edges may taper or be stepped in an overhang fashion, thereby permitting mechanical locking of the pad within the mold compound, Figs. 22, 26).
The combination of references fails to teach
the pad overhangs the solderable layer on at least three sides.
Zheng teaches
A method comprising:
the pad 102 overhangs 114 the layer 112 on at least three sides ([0031], [0032]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in the modified method of Shim. The motivation would be to improve mechanical retention of the pad in the mold compound as taught by Zheng.
Claim(s) 29, 31, 35 is/are rejected under 35 U.S.C. 103 as being obvious over Shim in view of Rogren as applied to claim 28 above, and further in view of Truhitte.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The combination of references fails to teach
29. (Previously Presented) The method of claim 28, wherein a semiconductor package of the plurality of semiconductor packages is a chip-on-lead package.
The combination of references fails to teach
31. (Currently Amended) The method of claim 28, wherein the plurality of pre-plated pads comprise a plurality of wettable flanks in each semiconductor package of the plurality of semiconductor packages.
The combination of references fails to teach
35. (New) The method of claim 28, wherein the solderable layer of each pre-plated pad is exposed on at least two sides of each semiconductor package of the plurality of semiconductor packages.
Truhitte teaches
A method comprising:
wherein the plurality of pre-plated pads 102 / 104 form a plurality of wettable flanks 124 ([0026], [0031]) in each semiconductor package of the plurality of semiconductor packages 122;
wherein a semiconductor package of the plurality of semiconductor packages ([0032], [0074]) comprises a chip-on-lead package;
wherein the solderable layer 124 of each pre-plated pad 102 / 104 is exposed on at least two sides of each semiconductor package of the plurality of semiconductor packages ([0031], [0074]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in the modified method of Shim. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04. Also, providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Claim(s) 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren as applied to claim 28 above, and further in view of Krishnan.
The combination of references fails to teach
32. (Previously Presented) The method of claim 28, wherein a semiconductor package of the plurality of semiconductor packages comprises a multi-die module package.
Krishnan teaches (Figs. 9, 10)
A method comprising:
wherein the semiconductor package of the plurality of semiconductor packages 102 comprises a multi-chip module package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a multi-chip module package in the modified method of Shim. The motivation would be mere duplication of parts based on engineering design considerations as taught by Krishnan ([0036]-[0041]). See MPEP 2144.04.
Claim(s) 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren and Krishnan as applied to claim 32 above, and further in view of U.S. Patent Application Publication No. 2010/0258925 (Jeon).
The combination of references fails to teach
33. (Previously Presented) The method of claim 32, wherein each die of the multi-die package are wire bonded to one another.
Jeon teaches (1E, 1F, 1J, 2A-2C)
A method comprising:
wherein each die 604 / 606 of the multi-die package are wire bonded 616 to one another ([0119]-[0129], [0135]-[0139]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to wire bond dies to one another in the modified method of Shim. The motivation would be based on engineering design considerations as taught by Jeon ([0036]-[0041]). See MPEP 2144.04. Further, the improved dual row MLP package allows for a higher pin count given the same package size, without sacrificing thermal performance. The improved dual row MLP package is also smaller than comparable packages with the same number of pins without sacrificing thermal performance ([0134]).
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren as applied to claim 28 above, and further in view of U.S. Patent Application Publication No. 2004/0097086 (Igarishi).
The combination of references fails to teach
34. (Currently Amended) The method of claim 28, wherein removing the metal carrier comprises etching the metal carrier to an etch stop layer comprised in the plurality of pre-plated pads.
Igarishi teaches
A method comprising:
wherein removing the carrier 11 comprises removing the carrier 11 by etching the carrier to an etch stop layer 12 / 16/ 24 comprised in the plurality of pads 12 / 14 / 15A / 16 ([0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an etch stop layer in the modified method of Shim. The motivation would be to provide pads with an anchoring effect to avoid distortion and improve support strength as taught by Igarashi ([0012], [0050], [0051], [0068]).
Claim(s) 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Rogren and Krishnan as applied to claim 32 above, and further in view of U.S. Patent Application Publication No. 2015/0187746 (Hsu) and Lee.
The combination of references fails to teach
36. (New) The method of claim 1, further comprising forming the pre-plated pad carrier by:
patterning a first layer of photoresist coupled over the metal carrier;
electroplating the solderable layer over the metal carrier;
patterning a second layer of photoresist coupled over the first layer of photoresist;
electroplating the wire bondable layer over the solderable layer; and
removing both the first layer of photoresist and the second layer of photoresist.
Hsu teaches
A method comprising:
patterning 160a, 160b a first layer of photoresist 158 coupled over the metal carrier 156;
electroplating 163 the first layer 104 over the metal carrier 156;
patterning a second layer of photoresist 162 coupled over the first layer of photoresist 158;
electroplating 165 the second bondable layer 106 over the first layer 104; and
removing both the first layer of photoresist 158 and the second layer of photoresist 162 ([0060]).
Lee teaches
A method comprising:
a wire bondable layer 106 over a solderable layer 104.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to employ a two-stage photoresist / electroplating process in the modified method of Shim. The motivation would be to permit independently controlled formation of vertically stacked plated portion. Further, a stacked pad provides solder functionality while directly overlying a layer as a surface suitable for wire bonding, thereby providing a plated pad having both functionality as taught by Lee ([0014]-[0017]). In addition, reduction in die size is allowed by the placing of bond pads over the active devices. Furthermore, there are no restrictions on underlying interconnect metal routing and the composite pad provides for absorption of force during wire bonding ([0107], [0108]).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Application Publication Nos. 2009/0102029 (Tadaoka), 2002/0003292 (Abbott), U.S. Patent No. 8,089,159 (Park) teach a method of forming a semiconductor package on a pre-plated pad carrier having a pad stack.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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