DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 have been considered but are moot because the new ground of rejection relies on a new reference for teaching matters specifically challenged in the argument.
Claim Objections
Claim 27 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 23. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 21-34 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claims 1, 21, 28, the terminology: “directly over” is ambiguous as to whether the plurality of die are vertically aligned to the plurality of pads, or physically contacting, or merely positioned above them.
The other claims are rejected as being dependent on one of claims 1, 21, 28.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are, to the extent taught and understood, rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Application Publication No. 2014/0084435 (Kimura).
Kimura discloses (Figs. 2a-2h)
1. (Currently Amended) A method of forming a semiconductor package comprising:
coupling a plurality of die 11 directly over and to a plurality of pads 12 / 13 of a pad carrier 15, the pad carrier 15 comprising a carrier 15 coupled to the plurality of pads 12 / 13 ([0040]);
wire bonding 14 the plurality of die 11 to the plurality of pads 13 ([0040]);
applying a mold compound 16 over the plurality of die 11 ([0041]);
removing the carrier 15 ([0042]-[0045]); and
singulating a plurality of semiconductor packages 11 after the carrier is removed ([0046]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2004/0097086 (Igarishi).
Kimura fails to disclose
2. (Original) The method of claim 1, wherein each pad of the plurality of pads comprises an etch stop layer directly coupled to the carrier, a solderable layer directly coupled to the etch stop layer, and a wire bondable layer directly coupled to the solderable layer.
Igarishi teaches
A method comprising:
wherein each pad of the plurality of pads 12 / 14 / 15A / 16 comprises an etch stop layer 12 / 16 / 24 ([0061]) directly coupled to the carrier 11, a solderable layer 14 directly coupled to the etch stop layer 12 / 16 / 24, and a wire bondable layer 15A directly coupled to the solderable layer 14.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a stacked pad in Kimura. The motivation would be to provide pads with an anchoring effect to avoid distortion and improve support strength as taught by Igarashi ([0012], [0050], [0051], [0068])
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2009/0102028 (Krishnan), cited by Applicant (D4 in Search Report).
Kimura fails to disclose
3. (Currently Amended) The method of claim 1, wherein a semiconductor package of the plurality of semiconductor packages comprises a multi-chip module package.
Krishnan teaches (Figs. 9, 10)
A method comprising:
wherein the semiconductor package of the plurality of semiconductor packages 102 comprises a multi-chip module package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a multi-chip module package in Kimura. The motivation would be mere duplication of parts based on engineering design considerations as taught by Krishnan ([0036]-[0041]). See MPEP 2144.04.
Claim(s) 4, 5 is/are rejected under 35 U.S.C. 103 as being obvious over Kimura as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2018/0145013 (Truhitte), cited by Applicant (D1 in Search Report).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Kimura fails to disclose
4. (Original) The method of claim 1, wherein the plurality of pads form a plurality of wettable flanks in each semiconductor package of the plurality of semiconductor packages.
Kimura fails to disclose
5. (Currently Amended) The method of claim 1, wherein the a semiconductor package of the plurality of semiconductor packages comprises a chip-on-lead package.
Truhitte teaches
A method comprising:
wherein the plurality of pads 102 / 104 form a plurality of wettable flanks 124 ([0026], [0031]) in each semiconductor package of the plurality of semiconductor packages 122;
wherein the a semiconductor package of the plurality of semiconductor packages ([0074]) comprises a chip-on-lead package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in Kimura. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04. Also, providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Claim(s) 21, 22 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of U.S. Patent Application Publication No. 2010/0258925 (Jeon).
Kimura discloses (Figs. 2a-2h)
21. (New) A method of forming a semiconductor package comprising:
coupling a plurality of die 11 directly over and to a plurality of pads 12 / 13 of a pad carrier 15, the pad carrier 15 comprising a carrier 15 coupled to the plurality of pads 12 /13 ([0040]);
wire bonding 14 the plurality of die 11 to the plurality of pads 13 ([0040]);
applying a mold compound 16 over the plurality of die 11 ([0041]);
removing the carrier 15 ([0042]-[0045]); and
singulating a plurality of semiconductor packages 11.
Kimura fails to disclose
wherein each die of the plurality of die is directly coupled over and to two pads of the plurality of pads.
Jeon teaches (Figs. 1E, 1F, 1J, 2A-2C)
A method comprising:
wherein each die 710 of the plurality of die is directly coupled over and to two pads 720 (a) of the plurality of pads ([0119]-[0129], [0135]-[0139]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a die coupled over and to two pads in Kimura. The motivation would be mere duplication of parts based on engineering design considerations as taught by Jeon ([0036]-[0041]). See MPEP 2144.04. Further, the improved dual row MLP package allows for a higher pin count given the same package size, without sacrificing thermal performance. The improved dual row MLP package is also smaller than comparable packages with the same number of pins without sacrificing thermal performance ([0134]).
Jeon teaches
22. (New) The method of claim 21, wherein wire bonding 711 the plurality of die 710 to the plurality of pads 720(a) comprises wire bonding 711 the plurality of die 710 to the plurality of pads 720(a) directly under the plurality of die 710.
Claim(s) 23-27 is/are rejected under 35 U.S.C. 103 as being obvious over Kimura in view of Jeon as applied to claim 21 above, and further in view Truhitte.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
The combination of references fails to teach
23. (New) The method of claim 21, wherein a semiconductor package of the plurality of semiconductor packages comprises a chip-on-lead package.
The combination of references fails to teach
24. (New) The method of claim 21, wherein each pad of the plurality of pads in each semiconductor package of the plurality of semiconductor packages comprises a wettable flank.
The combination of references fails to teach
27. (New) The method of claim 21, wherein a semiconductor package of the plurality of semiconductor packages comprises a chip-on-lead package.
Truhitte teaches
A method comprising:
wherein the plurality of pads 102 / 104 form a plurality of wettable flanks 124 ([0026], [0031]) in each semiconductor package of the plurality of semiconductor packages 122;
wherein the a semiconductor package of the plurality of semiconductor packages ([0074]) comprises a chip-on-lead package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a plurality of wettable flanks and a chip-on-lead package in the modified method of Kimura. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04. Also, providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Truhitte teaches (Fig. 6b)
25. (New) The method of claim 21, wherein the plurality of pads 220 / 222 / 22 has a first layer 222 and a second layer 22.
Truhitte teaches (Fig. 6b)
26. (New) The method of claim 25, wherein the first layer 222 overhangs the second layer 22 and forms a mold lock ([0011]).
Claim(s) 28, 29, 31 is/are, to the extent taught and understood, rejected under 35 U.S.C. 103 as being obvious over Kimura in view Truhitte.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Kimura discloses
28. (New) A method of forming a semiconductor package comprising:
coupling a plurality of die 11 directly over and to a plurality of pads 12 / 13 of a pad carrier 15, the pad carrier 15 comprising a carrier 15 coupled to the plurality of 12 / 13 ([0040]);
wire bonding 14 the plurality of die 11 to the plurality of pads 13 ([0040]);
applying a mold compound 16 over the plurality of die 11 ([0041]);
removing the carrier 15 ([0042]-[0045]); and
singulating a plurality of semiconductor packages 11.
Kimura fails to disclose
wherein the plurality of pads has a first layer and a second layer; and
wherein the first layer overhangs the second layer and forms a mold lock.
Truhitte teaches (Fig. 6b)
A method comprising:
wherein the plurality of pads 220 / 222 / 22 has a first layer 222 and a second layer 22; and
wherein the first layer 222 overhangs the second layer 22 and forms a mold lock ([0011]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a first layer, a second layer, and a mold lock in Kimura. The motivation would be to form a filleted solder connection that is visually verifiable for inspecting for a good electrical connection as taught by Truhitte ([0033]). See MPEP 2144.04.
Truhitte teaches
29. (New) The method of claim 28, wherein a semiconductor package of the plurality of semiconductor packages is a chip-on-lead package ([0074]).
Providing a chip-on-lead package would merely be a matter of routine engineering considerations based on suitability for an intended use. See MPEP 2144.07.
Truhitte teaches
31. (New) The method of claim 28, wherein the plurality of pads 102 / 104 comprise a plurality of wettable flanks in each semiconductor package of the plurality of semiconductor packages 122 ([0026], [0031]).
Claim(s) 30, 32, 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Truhitte as applied to claim 28 above, and further in view of Jeon.
The combination of references fails to teach
30. (New) The method of claim 28, wherein each die of the plurality of die is directly coupled over and to two pads of the plurality of pads.
Jeon teaches (1E, 1F, 1J, 2A-2C)
A method comprising:
wherein each die 710 of the plurality of die is directly coupled over and to two pads 720 (a) of the plurality of pads ([0119]-[0129], [0135]-[0139]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a die coupled over and to two pads in the modified method of Kimura. The motivation would be mere duplication of parts based on engineering design considerations as taught by Jeon ([0036]-[0041]). See MPEP 2144.04. Further, the improved dual row MLP package allows for a higher pin count given the same package size, without sacrificing thermal performance. The improved dual row MLP package is also smaller than comparable packages with the same number of pins without sacrificing thermal performance ([0134]).
Jeon teaches (Figs. 24A-24C)
32. (New) The method of claim 28, wherein a semiconductor package of the plurality of semiconductor packages comprises a multi-die module package.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a multi-chip module package in the modified method of Kimura. The motivation would be mere duplication of parts based on engineering design considerations as taught by Jeon ([0323]-[0330]). See MPEP 2144.04.
Jeon teaches
33. (New) The method of claim 32, wherein each die 604 / 606 of the multi-die package are wire bonded 616 to one another.
Claim(s) 34 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura in view of Truhitte as applied to claim 28 above, and further in view of Igarishi.
The combination of references fails to teach
34. (New) The method of claim 28, wherein removing the carrier comprises removing the carrier by etching the carrier to an etch stop layer comprised in the plurality of pads.
Igarishi teaches
A method comprising:
wherein removing the carrier 11 comprises removing the carrier 11 by etching the carrier to an etch stop layer 12 / 16/ 24 comprised in the plurality of pads 12 / 14 / 15A / 16 ([0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an etch stop layer in the modified method of Kimura. The motivation would be to provide pads with an anchoring effect to avoid distortion and improve support strength as taught by Igarashi ([0012], [0050], [0051], [0068])
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2012/0043660 (Poddar), 2023/0317567 (Huang), JP Publication No. 2004327903 (Masuda) teach a method of forming a semiconductor package.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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