DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the objection to the drawings, Applicant’s arguments and/or amendments have resolved the prior issues of claimed subject matter not being shown in the drawings. Accordingly, the objection to the drawings is withdrawn.
RE: the rejection of claim(s) 1-2, 4-9 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-2, 4-9 has been withdrawn.
RE: the rejection of claim(s) under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new ground of rejection presented herein.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 2, 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 26, 27 include “an approximately lateral axis within the substrate region” and this is indefinite as the longitudinal axis of the substrate is not defined, rendering the lateral axis indefinite, and “approximately” renders the lateral axis further indefinite.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-2, 4, 7-9, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20180040547 A1 (“Zuo”) in view of US20040104449A1 (“Yoon”), further in view of US 20160086723 A1 (“Su”).
RE: Claim 1, Zuo discloses A semiconductor die package (100 in FIG. 1), comprising:
a substrate region (102; 102 is a silicon substrate, [0024]) including a first side (top side of 102) and a second side (bottom side of 102) opposite the first side;
an interconnect region (region between 102, 106) over the first side of the substrate region and comprising at least one metal layer (126, 127, [0025]);
a redistribution region (region under 102) under the second side of the substrate region and comprising at least one conductive layer (128, 129); and
at least two via structures (113, 114, 115) passing through the substrate region connecting the conductive layer in the redistribution region and the at least one metal layer in the interconnect region,
wherein the at least two via structures, the conductive layer, and the metal layer form an inductor (an inductor includes the metal structures 126-129 and the through-substrate vias 113-115, [0036]), and
wherein the inductor comprises:
a first portion (126, 127, 128, 129) in configured to conduct a first electrical current along a first path in a first direction and including a first plurality of segments (126, 127, 128, 129) in the interconnect region and the redistribution region (126-129 are metal structures, [0026] and would therefore would be configured to conduct / capable of conducting electrical current along a first path in a first direction).
Zuo does not explicitly disclose:
an inverse coupled structure comprising:
the first portion configured to conduct the first electrical current along the first path in the first direction and including the first plurality of segments in the interconnect region and the redistribution region; and
a second portion configured to conduct a second electrical current along a second path in a second direction that is opposite the first direction and including a second plurality of segments in the interconnect region and the redistribution region.
In the same field of endeavor, Yoon discloses
FIG. 11 is a perspective view of a three-dimensional suspended solenoid inductor 108 in accordance with another embodiment of the invention. For reference, the substrate is intentionally omitted in FIGS. 11-31, [0119].
Yoon further discloses by simply modifying the solenoid inductors structures proposed in FIG. 9, and FIGS. 11-13, e.g., not connecting the solenoid turns in one strand but alternating a fist turn 39 and a secondary turn 41 as shown in FIG. 15, a suspended three-dimensional solenoid transformer 112 having a low substrate loss, a low insertion loss, a wide passing frequency band and a high coupling coefficient can be manufactured, [0122].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductor formed by 113-115, 126-129 to include a first turn of 113-115, 126-129 alternating with a second turn of 113-115, 126-129 as taught by Yoon in order to result in low insertion loss, a wide passing frequency band and a high coupling coefficient. As a result, the first turn and second turn would have a respective plurality of segments 126, 127, 128, 129 in the interconnect region and redistribution region.
In the same field of endeavor, Su discloses The performance of the inductor structures of FIGS. 5A-5C can be improved by providing two inversely coupled inductors, [0049]. If connections to the respective windings such that the current in the respective windings flows in opposite directions, the flux created in the core by each winding will also be in opposite directions and will largely cancel. Compared with the structures shown in FIGS. 5A-5C, the inverse coupling provides two significant benefits. First, the equivalent transient inductance, which impacts the transient speed of the converter, becomes smaller than the equivalent steady-state inductance, which determines the steady-state ripple of the converter. Therefore, high transient response and high efficiency can be simultaneously obtained, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 to be inversely coupled so that respective currents in the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 are opposite in direction as taught by Su in order to obtain a high transient response and high efficiency. As the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 would form an inversely coupled inductor structure, under a broad reasonable interpretation, they are considered an inversely coupled structure of an inductor.
RE: Claim 2, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 1, wherein the inverse coupled structure is an approximately helical shaped structure dispersed along an approximately lateral axis within the substrate region (FIG. 15 Yoon shows the turns 39, 41 form an approximately helical shaped structure dispersed along an approximately lateral axis; Accordingly as modified, the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 form an approximately helical shaped structure dispersed along an approximately lateral axis within the substrate region 102).
RE: Claim 4, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 1, wherein the first path is a first approximately helical path; and wherein the second path is a second approximately helical path (FIG. 15 Yoon shows the turns 39, 41 are first and second approximately helical paths; Accordingly as modified, the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 are first and second approximately helical paths, respectively).
RE: Claim 7, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 1, wherein the inductor further comprises:
a shunting structure (metal bumps or balls attached to 228, 229, [0058]; The second semiconductor device 250 may be coupled to the interposer device 210 using one or more metal bumps (or balls) attached to one or more metal structures (e.g., the third metal structure 228 and the fourth metal structure 229, [0058]; Accordingly, it would have been obvious to couple a second semiconductor device with metal bumps or balls attached to 128, 129 in order to use 110 as an interposer enabling connections between the semiconductor device 250 and 112 as taught by Zuo, [0058]).
RE: Claim 8, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 7, wherein the shunting structure comprises:
the at least two via structures (113, 114, 115 are coupled to 128, 129 and are therefore considered to form part of the shunting structure).
RE: Claim 9, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 7, wherein the shunting structure comprises:
portions of two or more conductive layers (126, 127) within the interconnect region (126, 127 are coupled to 128, 129 and are therefore considered to form part of the shunting structure).
RE: Claim 26, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 1, wherein the first portion and the second portion are formed around an approximately lateral axis within the substrate region (FIG. 15 Yoon shows the turns 39, 41 are formed around an approximately lateral axis; Accordingly, as modified, the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 are formed around an approximately lateral axis).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, Su as applied to claim 1 and further in view of US20150348695A1 (“Kostelnik”).
RE: Claim 6, Zuo in view of Yoon, Su does not explicitly disclose The semiconductor die package of claim 1, wherein the inductor further comprises:
a magnetic core structure within the substrate region between the at least two via structures.
However, in the same field of endeavor, Kostelnik discloses As shown in FIG. 17, the winding portions 136 shown as an example extend through the core material 116, i.e., for example, through the paste 116, thus ensuring that, as the winding portions 136 pass through cavity 106, they are surrounded on all sides by core material 116, and are not lying only on one side of the core material 116, as in the case of a standard coil, [0114]. This has the special surprising advantage that the stray field generated by the resulting coil in the outer region is reduced since the core material 116 concentrates the lines of force along the longitudinal axis of the coil in the direction of the inside of the coil, [0115].
Kostelnik further teaches at least one coil which is integrated into a substrate, said substrate having a closed cavity holding ferromagnetic particles which form the core of the coil, with the windings of the coil being formed by first winding portions and by second winding portions, with several or all of the first winding portions passing through the cavity, [0066]. Accordingly, the core is magnetic.
Kostelnik further shows in FIG. 4, the core 116 in the substrate 100 and the top surface of the core 116 is aligned with a top surface of 100.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second turns to pass through a magnetic core in the substrate 102 as taught by Kostelnik in order to concentrate the lines of force along the longitudinal axis of the coil and to reduce the stray field. As a result, the magnetic core would be between the vias 113, 114, 115 in 102.
Claim(s) 10, 14, 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, further in view of Su.
RE: Claim 10, Zuo discloses A semiconductor die package (100 in FIG. 1), comprising:
a first semiconductor die (110, 113-115, 126-129; 102 is a silicon substrate, [0024]; 106 is a semiconductor layer, [0023]) comprising:
a substrate region (102);
an interconnect region (region between 102, 106) over the substrate region;
a via structure (113) passing through the substrate region; and
an inductor including a portion (113 and/or 114) formed in the substrate region (an inductor includes the metal structures 126-129 and the through-substrate vias 113-115, [0036]); and
a second semiconductor die (112, [0023]) bonded to the interconnect region of the first semiconductor die (semiconductor layer 106 is bonded to the substrate 102, [0029]; the semiconductor device 112 may be electrically coupled to the interposer device 110 (e.g., via at least one bonding pad, [0023]),
wherein the inductor comprises:
a first portion (126, 127) configured to conduct a first electrical current along a first path in a first direction and including a first plurality of segments (126, 127) in the interconnect region (126, 127 are metal structures, [0026] and would therefore would be configured to conduct / capable of conducting electrical current along a first path in a first direction).
Zuo does not explicitly disclose:
an inverse coupled structure comprising:
the first portion configured to conduct the first electrical current along the first path in the first direction and including the first plurality of segments in the interconnect region; and
a second portion configured to conduct a second electrical current along a second path in a second direction that is opposite the first direction and including a second plurality of segments in the interconnect region.
In the same field of endeavor, Yoon discloses
FIG. 11 is a perspective view of a three-dimensional suspended solenoid inductor 108 in accordance with another embodiment of the invention. For reference, the substrate is intentionally omitted in FIGS. 11-31, [0119].
Yoon further discloses by simply modifying the solenoid inductors structures proposed in FIG. 9, and FIGS. 11-13, e.g., not connecting the solenoid turns in one strand but alternating a fist turn 39 and a secondary turn 41 as shown in FIG. 15, a suspended three-dimensional solenoid transformer 112 having a low substrate loss, a low insertion loss, a wide passing frequency band and a high coupling coefficient can be manufactured, [0122].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductor formed by 113-115, 126-129 to include a first turn of 113-115, 126-129 alternating with a second turn of 113-115, 126-129 as taught by Yoon in order to result in low insertion loss, a wide passing frequency band and a high coupling coefficient. As a result, the first turn and second turn would have a respective plurality of segments 126, 127 in the interconnect region.
In the same field of endeavor, Su discloses The performance of the inductor structures of FIGS. 5A-5C can be improved by providing two inversely coupled inductors, [0049]. If connections to the respective windings such that the current in the respective windings flows in opposite directions, the flux created in the core by each winding will also be in opposite directions and will largely cancel. Compared with the structures shown in FIGS. 5A-5C, the inverse coupling provides two significant benefits. First, the equivalent transient inductance, which impacts the transient speed of the converter, becomes smaller than the equivalent steady-state inductance, which determines the steady-state ripple of the converter. Therefore, high transient response and high efficiency can be simultaneously obtained, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 to be inversely coupled so that respective currents in the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 are opposite in direction as taught by Su in order to obtain a high transient response and high efficiency. As the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 would form an inversely coupled inductor structure, under a broad reasonable interpretation, they are considered an inversely coupled structure of an inductor.
RE: Claim 14, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 10, wherein the first semiconductor die further comprises:
a redistribution region (region below 102), and
wherein the inductor comprises:
another portion (128, 129) within the redistribution region.
RE: Claim 27, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 10, wherein the first portion and the second portion are formed around an approximately lateral axis within the substrate region (In FIG. 15 Yoon, the first turns 39, 41 are formed an approcimately lateral axis; Accordingly, as modified, the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 would be formed around an approximately lateral axis within the substrate region 102).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, Su as applied to claim 10 and further in view of US20220021348 A1 (“Philpott”), further in view of US20220320019A1 (“Chang”).
RE: Claim 11, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 10, wherein the first semiconductor die further comprises:
a capacitor structure (118, [0036]), and a switching device (116, The means for switching may include or correspond to the transistor 116 of FIG. 1, [0085]).
Zuo in view of Yoon, Su does not explicitly disclose:
the capacitor structure is a trench capacitor structure;
the switching device connects the trench capacitor structure and the inductor.
In the same field of endeavor, Philpott discloses a power supply circuit to provide a variable supply voltage (e.g., V.sub.CC) to a power amplifier (PA) for power efficiency, [0020], and a low pass filter implemented with an inductor-capacitor (LC) circuit may be coupled to the output of the power supply circuit in order to reduce the ripple on the output voltage from the power supply circuit on the PA, [0020].
Philpott further discloses switching circuitry, such as two transistors coupled in series between the inductor and capacitor of the LC circuit, may be used to disconnect and connect the low pass filter from the PA, [0020].
Philpott further discloses certain voltages may be applied to various nodes of the switching circuitry to allow the capacitor of the LC circuit to safely discharge without overstressing the other circuitry coupled to the capacitor, such as the switching circuitry, [0021].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the transistor/switching device 116 to connect the capacitor 118 with the inductor as taught by Philpott to allow the capacitor of the LC circuit to safely discharge without overstressing the other circuitry coupled to the capacitor.
In the same field of endeavor, Chang discloses the integrated component 400 may be referred to as an interconnecting die with integrally formed capacitors, and the integrated components 400 can increase the communication bandwidth between the first die 310, the second die 320, and the third die 330 while maintaining low contact resistance and high reliability. For example, the deep trench capacitors in the integrated component 400 may be formed of hafnium (Hf)-based materials, and the deep trench capacitor may have a permittivity of larger than 5ε0, but not limited thereto, [0022].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the capacitor 118 to be a deep trench capacitor as taught by Chang increase communication bandwidth and permittivity of the capacitor.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, Su as applied to claim 10 and further in view of Chang.
RE: Claim 12, Zuo in view of Yoon, Su does not explicitly disclose The semiconductor die package of claim 10, wherein the second semiconductor die comprises:
logic circuitry.
However, in the same field of endeavor, Chang discloses The integrated circuit dies 300 may include one or more types of semiconductor dies, such as a logic die, [0019].
Chang further discloses the integrated circuit dies 300 includes at least a first die 310, a second die 320 and a third die 330. In some embodiments, the first, second and third dies 310, 320, 330 are different types of dies or have different functionalities. In some embodiments, the first die 310 includes a logic die, the second die 320 includes a power management die and the third die 330 includes a memory die, [0019].
Chang further teaches An LC filter is a low pass filter built with an inductor and capacitor(s), [0015].
Zuo teaches A filter (e.g., an inductive-capacitive (LC) filter) may include the inductor (e.g., the metal structures 126-129 and the through-substrate vias 113-115) and the capacitor 118, [0037].
Zuo further teaches 112 is a semiconductor die, [0023].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor die 112 to be a logic die as taught by Chang in order to control the filtering circuitry in 110. As 112 is a logic die, it would comprise logic circuitry.
RE: Claim 13, Zuo in view of Yoon, Su does not explicitly disclose The semiconductor die package of claim 10, wherein an inductance performance of the inductor is included in a range of approximately 0.1 nanohenrys to approximately 100 nanohenrys.
However, in the same field of endeavor, Chang teaches the inductance of the inductor 500 is 1 nH to 10 nH, [0062].
Chang further discloses An LC filter is a low pass filter built with an inductor and capacitor(s). The embedded inductor in the redistribution structure and the capacitors of the embedded integrate component form an efficient LC circuit to increase power efficiency of the semiconductor package, [0015].
Zuo teaches A filter (e.g., an inductive-capacitive (LC) filter) may include the inductor (e.g., the metal structures 126-129 and the through-substrate vias 113-115) and the capacitor 118, [0037].
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductance of the inductor to be 1 nH to 10 nH as taught by Chang in order to form an efficient LC circuit to increase power efficiency.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, Su as applied to claim 10 and further in view of Kostelnik.
RE: Claim 15, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 10, wherein the via structure is a first via structure (113 or 114 is a first via structure).
Zuo in view of Yoon, Su does not explicitly disclose the inductor further comprises:
a magnetic core structure between the first via structure and a second via structure.
However, in the same field of endeavor, Kostelnik discloses As shown in FIG. 17, the winding portions 136 shown as an example extend through the core material 116, i.e., for example, through the paste 116, thus ensuring that, as the winding portions 136 pass through cavity 106, they are surrounded on all sides by core material 116, and are not lying only on one side of the core material 116, as in the case of a standard coil, [0114]. This has the special surprising advantage that the stray field generated by the resulting coil in the outer region is reduced since the core material 116 concentrates the lines of force along the longitudinal axis of the coil in the direction of the inside of the coil, [0115].
Kostelnik further teaches at least one coil which is integrated into a substrate, said substrate having a closed cavity holding ferromagnetic particles which form the core of the coil, with the windings of the coil being formed by first winding portions and by second winding portions, with several or all of the first winding portions passing through the cavity, [0066]. Accordingly, the core is magnetic.
Kostelnik further shows in FIG. 4, the core 116 in the substrate 100 and the top surface of the core 116 is aligned with a top surface of 100.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second turns to pass through a magnetic core as taught by Kostelnik in order to concentrate the lines of force along the longitudinal axis of the coil and to reduce the stray field. As a result, the magnetic core would be between the vias 113, 114, 115.
Claim(s) 21, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, further in view of Su.
RE: Claim 21, Zuo discloses A semiconductor die package (100 in FIG. 1), comprising:
a semiconductor substrate (102 is a silicon substrate, [0024]);
a first conductive structure (126) disposed over the semiconductor substrate;
a second conductive structure (128) disposed under the semiconductor substrate;
a first interconnect structure (113) disposed through the semiconductor substrate and coupled to the second conductive structure;
a second interconnect structure (114) disposed through the semiconductor substrate and coupled to the first conductive structure and the second conductive structure (an inductor includes the metal structures 126-129 and the through-substrate vias 113-115, [0036]; Accordingly, 126-129, 113-115 are coupled to each other),
wherein the first interconnect structure, the second interconnect structure, the first conductive structure, and the second conductive structure form a first portion of an inductor (an inductor includes the metal structures 126-129 and the through-substrate vias 113-115, [0036]);
wherein the first portion is configured to conduct a first electrical current along a first path in a first direction (126-129 are metal structures, vias 113-115 are metal, [0026], [0027], and would therefore would be configured to conduct / capable of conducting electrical current along a first path in a first direction).
Zuo does not explicitly disclose:
a third conductive structure disposed over the semiconductor substrate;
a fourth conductive structure disposed under the semiconductor substrate;
a third interconnect structure disposed through the semiconductor substrate and coupled to the fourth conductive structure; and
a fourth interconnect structure disposed through the semiconductor substrate and coupled to the third conductive structure and the fourth conductive structure,
wherein the third interconnect structure, the fourth interconnect structure, the third conductive structure, and the fourth conductive structure form a second portion of an inductor, and
wherein the second portion is configured to conduct a second electrical current along a second path in a second direction that is opposite the first direction.
In the same field of endeavor, Yoon discloses
FIG. 11 is a perspective view of a three-dimensional suspended solenoid inductor 108 in accordance with another embodiment of the invention. For reference, the substrate is intentionally omitted in FIGS. 11-31, [0119].
Yoon further discloses by simply modifying the solenoid inductors structures proposed in FIG. 9, and FIGS. 11-13, e.g., not connecting the solenoid turns in one strand but alternating a fist turn 39 and a secondary turn 41 as shown in FIG. 15, a suspended three-dimensional solenoid transformer 112 having a low substrate loss, a low insertion loss, a wide passing frequency band and a high coupling coefficient can be manufactured, [0122].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inductor formed by 113-115, 126-129 to include a first turn of 113-115, 126-129 alternating with a second turn of 113-115, 126-129 as taught by Yoon in order to result in low insertion loss, a wide passing frequency band and a high coupling coefficient. As a result, the first turn and second turn would have a respective plurality of segments 126, 127, 128, 129 in the interconnect region and redistribution region. The first turn corresponds to the claimed first portion of the inductor.
In the same field of endeavor, Su discloses The performance of the inductor structures of FIGS. 5A-5C can be improved by providing two inversely coupled inductors, [0049]. If connections to the respective windings such that the current in the respective windings flows in opposite directions, the flux created in the core by each winding will also be in opposite directions and will largely cancel. Compared with the structures shown in FIGS. 5A-5C, the inverse coupling provides two significant benefits. First, the equivalent transient inductance, which impacts the transient speed of the converter, becomes smaller than the equivalent steady-state inductance, which determines the steady-state ripple of the converter. Therefore, high transient response and high efficiency can be simultaneously obtained, [0049].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 to be inversely coupled so that respective currents in the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 are opposite in direction as taught by Su in order to obtain a high transient response and high efficiency. As the first turn of 113-115, 126-129 and the second turn of 113-115, 126-129 would form an inversely coupled inductor structure, under a broad reasonable interpretation, they are considered an inversely coupled structure of an inductor.
Modified Zuo would therefore disclose:
a third conductive structure (second turn would include another 126) disposed over the semiconductor substrate;
a fourth conductive structure (second turn would include another 128) disposed under the semiconductor substrate;
a third interconnect structure (second turn would include another 113) disposed through the semiconductor substrate and coupled to the fourth conductive structure; and
a fourth interconnect structure (second turn would include another 114) disposed through the semiconductor substrate and coupled to the third conductive structure and the fourth conductive structure,
wherein the third interconnect structure, the fourth interconnect structure, the third conductive structure, and the fourth conductive structure form a second portion of an inductor (As modified, the second turn of 113-115, 126-129 would form another inductor), and
wherein the second portion is configured to conduct a second electrical current along a second path in a second direction that is opposite the first direction (As modified, the currents in the first and second portions of the inductor are opposite in direction).
RE: Claim 25, Zuo in view of Yoon, Su discloses The semiconductor die package of claim 21, wherein the first path and the second paths are approximately helical paths.
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuo in view of Yoon, Su as applied to claim 21 and further in view of Kostelnik.
RE: Claim 22, Zuo in view of Yoon, Su does not explicitly disclose The semiconductor die package of claim 21, further comprising a magnetic core structure disposed in the semiconductor substrate between the first interconnect structure and the second interconnect structure.
However, in the same field of endeavor, Kostelnik discloses As shown in FIG. 17, the winding portions 136 shown as an example extend through the core material 116, i.e., for example, through the paste 116, thus ensuring that, as the winding portions 136 pass through cavity 106, they are surrounded on all sides by core material 116, and are not lying only on one side of the core material 116, as in the case of a standard coil, [0114]. This has the special surprising advantage that the stray field generated by the resulting coil in the outer region is reduced since the core material 116 concentrates the lines of force along the longitudinal axis of the coil in the direction of the inside of the coil, [0115].
Kostelnik further teaches at least one coil which is integrated into a substrate, said substrate having a closed cavity holding ferromagnetic particles which form the core of the coil, with the windings of the coil being formed by first winding portions and by second winding portions, with several or all of the first winding portions passing through the cavity, [0066]. Accordingly, the core is magnetic.
Kostelnik further shows in FIG. 4, the core 116 in the substrate 100 and the top surface of the core 116 is aligned with a top surface of 100.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the first and second turns to pass through a magnetic core in the substrate 102 as taught by Kostelnik in order to concentrate the lines of force along the longitudinal axis of the coil and to reduce the stray field. As a result, the magnetic core would be between the vias 113, 114, 115 in 102.
RE: Claim 23, Zuo in view of Yoon, Su, Kostelnik discloses The semiconductor die package of claim 22, wherein the magnetic core structure extends partially through the semiconductor substrate (As modified, the magnetic core would be in the substrate 102 and therefore extend partially through 102).
RE: Claim 24, Zuo in view of Yoon, Su, Kostelnik discloses The semiconductor die package of claim 23, wherein a top surface of the magnetic core structure is aligned with a top surface of the semiconductor substrate (As modified, the top surface of the magnetic core is aligned with a top surface of the semiconductor substrate 102).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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