DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-5 and 15-20 in the reply filed on 12/05/2025 is acknowledged. New claims 21-29 are further included with the elected invention and have been considered.
Claims 6-14 are non-elected and have been treated as canceled as confirmed by Applicant’s representative. See the attached interview summary.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Ohara et al. (JP 5206311).
In reference to claim 1, Roy et al. (US 2024/0234158), hereafter “Roy,” discloses a semiconductor structure, with reference to Figure 6, comprising:
at least one etch stop layer (ESL) 320, paragraph 26; and
a silicon operational structure 310A, over the at least one ESL, paragraph 30, that includes a first isolation structure 360B associated with a first width and a second isolation structure 360a associated with a second width larger than the first width, paragraph 2 (“trenches, later filled with oxide”).
Roy does not disclose wherein sidewall surfaces of the first isolation structure include a scallop profile.
Ohara et al. (JP 5206311), hereafter “Ohara,” a machine translation of which is included herewith and cited herein, discloses a semiconductor structure including teaching sidewall surfaces of the first isolation structure include a scallop profile, middle trench in Figure 1(g). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the sidewall surfaces of the first isolation structure to include a scallop profile. One would have been motivated to do so in order to form the first isolation structure by a cyclic etch process, paragraph 13, as is suggested by Roy, paragraph 56.
In reference to claim 3, Roy discloses the second isolation structure is adjacent to a line 310A in Figure 6, that is associated with a third width smaller than the second width.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Ohara et al. (JP 5206311) as applied to claim 1 above and further in view of Chen et al. (US 2006/0091461).
In reference to claim 2, Roy does not disclose an oxide material on sidewall surfaces of the first isolation structure and on sidewall surfaces of the second isolation structure wherein the oxide material is absent from bottom surfaces of the first isolation structure and the second isolation structure.
Chen et al. (US 2006/0091461), hereafter “Chen,” discloses a semiconductor device including teaching an oxide material, 46 in Figure 7, on sidewall surfaces of the first isolation structure and on sidewall surfaces of the second isolation structure wherein the oxide material is absent from bottom surfaces of the first isolation structure and the second isolation structure, paragraph 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for an oxide material to be on sidewall surfaces of the first isolation structure and on sidewall surfaces of the second isolation structure wherein the oxide material is absent from bottom surfaces of the first isolation structure and the second isolation structure. One would have been motivated to do so in order to reduce defects and protect the silicon, id.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Ohara et al. (JP 5206311) as applied to claim 3 above and further in view of Assefa et al. (US 8,525,264).
In reference to claim 4, Roy does not disclose the third width is in a range from approximately 0.3 micrometers (µm) to approximately 10 µm.
Assefa et al. (US 8,525,264), hereafter “Assefa,” discloses a semiconductor device including teaching features defined between isolation structures with a third width in a range from approximately 0.3 micrometers (µm) to approximately 10 µm, (300 nm to 6,000 nm) col. 6 lines 1-17. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the third width to be in a range from approximately 0.3 micrometers (µm) to approximately 10 µm. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case applying the isolation structures of Roy to the silicon waveguide 32 in Figure 1, defined by isolation structures 22 of Assefa.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Ohara et al. (JP 5206311) as applied to claim 1 above and further in view of Donohue et al. (US 6,071,822).
In reference to claim 5, Roy does not disclose a lower portion of the second isolation structure is wider than the second width, and the lower portion is approximately 30 nanometers or less in height.
Donohue et al. (US 6,071,822) discloses a semiconductor device including teaching a lower portion of the second isolation structure is wider than the second width, and the lower portion is approximately 30 nanometers or less in height, ‘undercut’ of trenches at left in Figure 4. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the lower portion of the second isolation structure to be wider than the second width, and the lower portion is approximately 30 nanometers or less in height. One would have been motivated to do so in order to use a fluorochemical etch chemistry to quickly and safely etch structural features, col. 1 lines 55-65.
Claims 15 and 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Chen et al. (US 2006/0091461).
In reference to claim 15, Roy discloses a semiconductor structure, with reference to Figure 6, comprising:
at least one etch stop layer (ESL) 320, paragraph 26; and
a silicon operational structure 310A, over the at least one ESL, paragraph 30, that includes a first isolation structure 360B associated with a first width and a second isolation structure 360a associated with a second width larger than the first width, paragraph 2 (“trenches, later filled with oxide”).
Roy does not disclose an oxide material on sidewall surfaces of the first isolation structure and the second isolation structure and absent from bottom surfaces of the first isolation structure and the second isolation structure.
Chen et al. (US 2006/0091461), hereafter “Chen,” discloses a semiconductor device including teaching an oxide material, 46 in Figure 7, on sidewall surfaces of the first isolation structure and the second isolation structure and absent from bottom surfaces of the first isolation structure and the second isolation structure, paragraph 25. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for an oxide material to be on sidewall surfaces of the first isolation structure and the second isolation structure and absent from bottom surfaces of the first isolation structure and the second isolation structure. One would have been motivated to do so in order to reduce defects and protect the silicon, id.
In reference to claim 17, Roy discloses the first isolation structure and the second isolation structure comprise at least one dielectric material, paragraph 2 (“trenches, later filled with oxide”).
In reference to claim 18, Roy discloses the first width is in a range from approximately 0.3 micrometers (µm) to approximately 1 µm, paragraph 15.
In reference to claim 19, Roy discloses the second width is in a range from approximately 1.0 µm to approximately 10 µm, paragraph 15.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Roy et al. (US 2024/0234158) in view of Chen et al. (US 2006/0091461) as applied to claim 15 above and further in view of Assefa et al. (US 8,525,264).
In reference to claim 16, Roy does not disclose the silicon operational structure comprises a waveguide.
Assefa et al. (US 8,525,264) discloses a semiconductor device including teaching a silicon operational structure comprises a waveguide, 32 in Figure 1, col. 4 line 58- col. 5 line 11. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the silicon operational structure to comprise a waveguide. To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D. In this case, applying the isolation trenches of Roy as the isolation trenches 22 of Assefa that define waveguide 32.
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2009/0072355) in view of Tilke et al. (US 2007/0059897).
In reference to claim 21, Cheng et al. (US 2009/0072355), hereafter “Cheng,” discloses a semiconductor structure, comprising:
a silicon layer 10 that includes, paragraph 56:
a first trench T2 associated with a first width w3 and a first depth d3, and
a second trench T1 associated with a second width w1, larger than the first width, and a second depth d1 less than the first depth, paragraph 73.
Cheng does not disclose an oxide material on sidewalls of the first trench and the second trench,
wherein the oxide material is absent from a bottom surface of the first trench and the second trench.
Tilke et al. (US 2007/0059897) discloses a semiconductor device including a first trench associated with a first width, and
a second trench associated with a second width, larger than the first width; and an oxide material, 460 in Figure 10, on sidewalls of the first trench and the second trench, wherein the oxide material is absent from a bottom surface of the first trench and the second trench, paragraph 34. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for an oxide material to be on sidewalls of the first trench and the second trench, wherein the oxide material is absent from a bottom surface of the first trench and the second trench. One would have been motivated to do so in order to protect the trench sidewalls from etching, paragraph 47.
In reference to claim 22, Cheng discloses a hard mask 20 on a top surface of the silicon layer 10, paragraph 57.
In reference to claim 23, Cheng discloses an isolation structure that fills the first trench and the second trench, 70B and 70A in Figure 11, paragraph 78.
In reference to claim 24, Cheng discloses the isolation structure comprises a dielectric material, paragraph 78.
Claims 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2009/0072355) in view of Tilke et al. (US 2007/0059897) as applied to claim 23 above and further in view of Hebert et al. (US 2011/0115047).
In reference to claim 25, Cheng discloses a hard mask 20 on a top surface of the silicon layer 10, paragraph 57.
Cheng does not disclose wherein the isolation structure is coplanar with the hard mask.
Hebert et al. (US 2011/0115047), hereafter “Hebert,” discloses a semiconductor device including teaching the isolation structure 86, 90 in Figure 9, is coplanar with the hard mask 82, paragraph 18. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the isolation structure to be coplanar with the hard mask. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. In this case substituting one isolation material configuration for another.
In reference to claim 26, Cheng does not disclose a supporting layer, wherein the silicon layer resides over the supporting layer.
Hebert teaches a supporting layer, 162 in Figure 17, wherein the silicon layer 164 resides over the supporting layer, paragraph 34. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for the semiconductor device to further include a supporting layer, wherein the silicon layer resides over the supporting layer. To do so would have merely been a simple substitution of one known element for another to obtain predictable results; KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385, (2007), MPEP 2143 I. B. in this case substituting one device base layer for another as suggested by Hebert between Figures 9 and 17 and paragraph 18.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US 2009/0072355) in view of Tilke et al. (US 2007/0059897) as applied to claim 23 above and further in view of Roy et al. (US 2024/0234158).
In reference to claim 29, Cheng does not disclose a ratio of the second width of the second trench relative to the first width of the first trench is in a range from approximately 1.1 to approximately 33.
Roy teaches a semiconductor device including teaching a ratio of the second width of the second trench relative to the first width of the first trench is in a range from approximately 1.1 to approximately 33, paragraph 15, ((s.sub.max may be between 16 times to 100 times s.sub.min”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention for a ratio of the second width of the second trench relative to the first width of the first trench to be in a range from approximately 1.1 to approximately 33. One would have been motivated to do so in order to concurrently form features of widely ranging dimensions, paragraph 15.
Allowable Subject Matter
Claims 20, 27, and 28 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first isolation structure extends into the at least one ESL lower than the second isolation structure; in combination with the other recited limitations in the respective claims and their base claims.
Claim 27 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the first trench extends into the supporting layer; in combination with the other recited limitations in the respective base claim.
Claim 28 would be allowable because the prior art of record fails to teach or fairly suggest the structure wherein the second trench resides directly on a top surface of the supporting layer; in combination with the other recited limitations in the respective base claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 6,306,723), Aoki et al. (US 2010/0244183), Chang et al. (US 2016/0027684), Enda et al. (US 2018/0358257), and Lerner (US 2011/0143519) disclose related isolation structures with multiple widths.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN R. JUNGE whose telephone number is (571)270-5717. The examiner can normally be reached M-F 8:00-4:30 CT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R JUNGE/ Primary Examiner, Art Unit 2897