Prosecution Insights
Last updated: April 18, 2026
Application No. 18/194,544

SEMICONDUCTOR ELEMENT WITH BONDING LAYER HAVING LOW-K DIELECTRIC MATERIAL

Final Rejection §102§103§112
Filed
Mar 31, 2023
Examiner
NGUYEN, NIKI HOANG
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Adeia Semiconductor Bonding Technologies Inc.
OA Round
2 (Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
833 granted / 919 resolved
+22.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
19 currently pending
Career history
938
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
39.2%
-0.8% vs TC avg
§102
35.7%
-4.3% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 919 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/03/2026 has been considered by the examiner. Response to Arguments Applicant's arguments on claims 7-16,18,19 and 26 filed on 01/12/2026 have been fully considered but they are not persuasive. The Applicant alleged that the low-K dielectric layer 106 is disposed about the first metal feature 108 instead of the contact pad of claim 7. The Examiner respectfully disagreed with the Applicant’s interpretation because the broad definition of “about” is near or close to. In fig. 1F, the low-K dielectric layer 106 is disposed near and/or close to the contact pad 120 and the dielectric barrier 114a. Thus, the Examiner believes the low-K dielectric layer 106 in the Chen reference still read on claim 7. Applicant’s arguments with respect to claims 1-5,28, 29 and 64 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 28 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims are generally narrative and indefinite, failing to conform with current U.S. practice. They appear to be a literal translation into English from a foreign document and are replete with grammatical and idiomatic errors. Regarding claim 28, the feature recites “wherein in a cross-sectional view of the device, a plane perpendicular to the upper hybrid bonding surface and intersecting the second dielectric layer intersects the second portion of the dielectric barrier layer and the first dielectric layer” found very grammatical issue. For the remainder of this Action, the Examiner interprets a plane perpendicular to the upper hybrid bonding surface and intersecting the second dielectric layer, wherein the plane further intersects the second portion of the dielectric barrier layer and the first dielectric layer. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the interconnect structure further comprising a conductive barrier layer disposed on the entire dielectric barrier layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. NOTE: In figs. 2A and 3, the conductive barrier layers 222, 226 and 228 placed on at the bottom of conductive features 212, 214 and 216. The Examiner is not clear which of the conductive barrier layers disposed on the entire dielectric barrier layer 242 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 7,8, 10-15,18-19 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 20190385963; hereinafter 20190385963). Regarding claim 7, Chen teaches an element comprising: an interconnect structure (130) having an upper hybrid bonding surface (refer to upper surface of 130); a contact pad (120) extending at least partially through the interconnect structure (130); a dielectric barrier layer (114a ) disposed on and covering entire sidewalls of the contact pad (120); and a low-k dielectric layer (106/122; see pars. 15 and 18) disposed about the contact pad (120) and the dielectric barrier layer (114a). Regarding claim 8, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Chen teaches the contact pad (120) is connected to an underlying conductive feature (refer to 108) with a first conductive barrier layer (110) disposed between the contact pad (120) and the underlying conductive feature (108). Regarding claim 10, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches a second conductive barrier layer (110) is disposed between the contact pad (120) and the intervening via portion (refer to one of the plugs of 108). Regarding claim 11, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches the low-k dielectric layer (106/122) extends to a depth covering the second conductive barrier layer (110), and wherein the dielectric barrier layer (114) is disposed on and covers entire sidewalls formed by the contact pad (120) and edges of the second conductive barrier layer (refer to edges of 110). Regarding claim 12, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches the low-k dielectric layer (106/122) extends to a depth covering a partial thickness of the underlying conductive feature (refer to 108) (see fig. 1G), and wherein the dielectric barrier layer (114) is disposed on and covers entire sidewalls formed by the contact pad (120), the intervening via portion (refer to plugs of 108) and the partial thickness of the underlying conductive feature (108). Regarding claim 13, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches the underlying conductive feature (108) is embedded in a first dielectric layer (106), and wherein the dielectric barrier layer (114) extends between the low-k dielectric layer (122) and the first dielectric layer (106). Regarding claim 14, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches the dielectric barrier layer (114) disposed on each sidewall has a corner (refer to bottom corner at each sidewall). Regarding claim 15, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches an approximately right angle turn (refer to bottom corner of 114) is formed in the dielectric barrier layer (114) between each sidewall (refer to sidewall of 114) and an interface between the low-k dielectric layer (122) and the first dielectric layer (106). Regarding claim 18, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches the contact pad (120) directly connects to the underlying conductive feature (108) without an intervening via portion. Regarding claim 19, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches an upper dielectric layer (122a) disposed on the low-k dielectric layer (122b), the upper dielectric layer (122a) forming at least part of the upper hybrid bonding surface. Regarding claim 26, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Fig. 1G of Chen teaches a second element (200b) comprising a third dielectric layer (refer to 222) and a second contact pad (refer to contact pad 210) at least partially embedded in the third dielectric layer (222), wherein the low-k dielectric layer (122) is directly bonded to the third dielectric layer (222) without an adhesive and the contact pad (110) is directly bonded to the second contact pad (refer to contact pad 210) without an adhesive (see fig. 1G). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen. Regarding claim 9, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above except for the contact pad is connected to the underlying conductive feature by way of an intervening via portion. Another embodiment of Chen teaches a conductor structure further includes a plurality of plugs and a plurality of conductive lines. One of the plugs may be electrically connected to one or more conductive lines (see par. 15). Thus, it would have been obvious to one having ordinary skills in the art before the invention was made to include e the contact pad is connected to the underlying conductive feature by way of an intervening via portion as taught in one of the embodiment of Chen in the teaching of Chen so that it provides an alternative way of making product. Claim 16 is rejected under 35 U.S.C. 102(a(1)) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Chen. Regarding claim 16, Chen teaches all the limitations of the claimed invention for the same reasons as set forth above. It should be known that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Since claim 16 is directed to a device, the method of the contact pad and the intervening via portion is not germane to the issue of patentability of the device itself. Therefore, the limitation of the contact pad and the intervening via portion are formed uniformly stated in claim 16 has not been given any patentable weight. MPEP 2113 [R-1]. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5, 28,29 and 64 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu (US 2014/0117546). Regarding claim 1, Liu teaches an element in figs.1 and 5A, comprising: a substrate (refer to 102; see par. 22 and fig. 1); an interconnect structure (refer to 106; see par. 24 and fig. 1) over the substrate (102), the interconnect structure (refer to the interconnect structure in wafer 100.sub.1 in fig. 5A) having at least one conductor (refer to 112.sub.2) at least partially embedded in a dielectric material (refer to 114.sub.T and 114.sub.U), the dielectric material (refer to 114.sub.T and 114.sub.U) comprising a first dielectric layer (refer to 114.sub.U) and a second dielectric layer (refer to 114.sub.T) disposed on the first dielectric layer (refer to 114.sub.U) ; a first dielectric barrier layer (refer to diffusion barrier layer 160.sub.B) disposed on and covering at least a portion of a sidewall of the at least one conductor (refer top sidewall of 112.sub.2) and extending between the first dielectric layer and the second dielectric layer (NOTE: Fig. 5A shows the horizontal portion of 160.sub.B is extending between the first dielectric layer 114.sub.U and the second dielectric layer 114.T); and a second conductive barrier layer (refer to layer 113) disposed on the first dielectric barrier layer (refer to 160.sub.B) (see fig. 5A). Regarding claim 2, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 5A of Liu teaches at least one conductor (112.sub.2) is completely buried in the dielectric material (refer to 114.sub.U and 114.sub.T). Regarding claim 3, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Liu teaches each of the at least one conductor comprises a contact pad (refer to 112.sub.2), the contact pad forming part of a hybrid bonding surface (see fig. 5A). Regarding claim 4, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Liu teaches each of the at least one conductor (refer to 112.sub.2) further comprises a via portion (110) connected to the contact pad (refer to 112.sub.2) (see par. 24). Regarding claim 5, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, Liu teaches the second dielectric layer (114) comprises a low-k dielectric material (see par. 24). Regarding claim 28, Liu teaches a device in figs. 1 and 5A comprising: a substrate (102 in fig. 1; see par. 22); an interconnect structure (106 see par. 22 and fig. 1) disposed on the substrate (102), the interconnect structure (refer to the interconnect structure in wafer 100.sub.1 in fig. 5A) having an upper hybrid bonding surface (refer to upper surface of 100.sub.1), the interconnect structure (refer to the interconnect structure in wafer 100.sub.1 in fig. 5A) comprising: a first dielectric layer (refer to 114.sub.U) disposed on the substrate (102 in fig. 1); a plurality of conductors (110 and 112.sub.2) at least partially embedded in the interconnect structure (refer to the interconnect structure in wafer 100.sub.1 in fig. 5A); a dielectric barrier layer (refer to diffusion barrier 160.sub.B) having a first portion (refer to lateral portion of 160.sub.B) disposed on and covering at least a portion of sidewalls of the plurality of the conductors (NOTE: fig. 5A shows the lateral portion of the diffusion barrier layer 160.sub.B disposed on and covering sidewalls of conductor 112.sub.2); a second dielectric layer (refer to 114.sub.T) disposed about the first portion of the dielectric barrier layer (refer to diffusion barrier 160.sub.B); and wherein a second portion of the dielectric barrier layer (refer to a horizontal portion of the diffusion barrier 160.sub.B) extends between the first dielectric layer and the second dielectric layer (refer to 114.sub.U and 114.sub.T), the second portion of the dielectric barrier layer (refer to the horizontal portion of the diffusion barrier 160.sub.B) is angled relative to the first portion of the dielectric barrier layer. (NOTE: the horizontal portion of the diffusion barrier 160.sub.B is angled at 90º relative to the lateral portions of the diffusion barrier 160.sub.B), wherein in a cross-sectional view of the device, a plane perpendicular to the upper hybrid bonding surface and intersecting the second dielectric layer intersects the second portion of the dielectric barrier layer and the first dielectric layer (NOTE: the P plane is labeled below perpendicular with an upper surface of the bonding surface and intersecting the 2nd dielectric layer, wherein the plane further intersects the horizontal portion of 160.sub.B and the first dielectric layer). PNG media_image1.png 588 743 media_image1.png Greyscale Regarding claim 29, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 5A of Liu shows the interconnect structure further comprising a conductive barrier layer (113) disposed on the entire dielectric barrier layer (refer to the diffusion barrier 160.sub.B). Regarding claim 64, Liu teaches all the limitations of the claimed invention for the same reasons as set forth above. Besides, fig. 5A of Liu teaches the second portion of the dielectric barrier layer (refer to the horizontal portion of the diffusion barrier 160.sub.B) the extends in contact with the first dielectric layer and the second dielectric layer (refer to 114.sub.U and 114.sub.T). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tram Hoang Nguyen whose telephone number is (571) 272-5526. The examiner can normally be reached on 6:00am-2:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Steven Loke can be reached on (703)872-9306. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NIKI H NGUYEN/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Mar 31, 2023
Application Filed
Aug 09, 2025
Non-Final Rejection — §102, §103, §112
Jan 12, 2026
Response Filed
Apr 04, 2026
Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
96%
With Interview (+5.1%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 919 resolved cases by this examiner. Grant probability derived from career allow rate.

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