DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s amendment of Claims 1-19 in the Applicant’s Remarks Made in an Amendment dated 03/16/2026 read upon Device Embodiment 10 which was elected in Applicant’s Arguments dated 08/07/2025. Therefore claims 1-19 are addressed in this Office Action.
Response to Arguments
Applicant’s arguments, see page 10-11 of Applicant’s Arguments, filed 03/16/2026, with respect to the rejection(s) of claim 20 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the prior rejection made in the office action mailed 12/18/2025 has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art reference Ema et al. (US 2005/0227440 A1) teaches a patterned photoresist feature as shown below. And Chuang et al. in view of Ema et al. (US 2010/000 Ema et al. (US 2005/0227440 A1) teaches the limitations of claim 20 as described below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7, 9-10, 14-15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang et al. (US 2011/0220963 A1, hereinafter Chuang ‘963).
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With respect to Claim 1 Chuang ‘963 discloses a semiconductor device comprising (Fig 1-4B):
a semiconductor substrate (45, Fig 3, Para [0070]);
a first sub-portion (first sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 1SP), a second sub-portion (second sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 2SP), a third sub-portion (third sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 3SP), and a fourth sub-portion (fourth sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 4SP) of a portion (90/100, Fig 4A, Para [0016]) of the semiconductor substrate (45), wherein the first sub-portion (1SP) circumscribes (1SP circumscribing 2SP, 3SP and 4SP shown in annotated Fig 4A/4B of Chuang ‘963) the second sub-portion (2SP), the third sub-portion (3SP), and the fourth sub-portion (4SP);
a first isolation structure (50, Fig 4A, Para [0015]) disposed in the semiconductor substrate (45), wherein the first isolation structure (50) circumscribes (50 circumscribing 1SP (1SP is within structure 50 as shown in annotated Fig 4A/4B) disclosed in annotated Fig 4A/4B of Chuang ‘963) the first sub-portion (1SP);
a second isolation structure (51, Fig 4A, Para [0015]) disposed in the semiconductor substrate (45), wherein the second isolation structure (51) circumscribes (51 circumscribing 2SP, 3SP and 4SP disclosed in annotated Fig 4A/4B of Chuang ‘963) the second sub-portion (2SP), the third sub-portion (3SP), and the fourth sub-portion (4SP), and further wherein the first sub-portion (1SP) is disposed between (1SP between 51 and 50 disclosed in annotated Fig 4A/4B of Chuang ‘963) the second isolation structure (51) and the first isolation structure (50);
a first blocking structure (140, Fig 4A, Para [0018]) and a second blocking structure (141, Fig 4A, Para [0018]) disposed over (Fig 4A discloses 140 and 141 are over 50) the first isolation structure (50), wherein the first blocking structure (140) is oriented lengthwise (140 extending lengthwise in a first direction shown in annotated Fig 4A/4B of Chuang ‘963) along a first direction (first direction shown in annotated Fig 4A/4B of Chuang ‘963, hereinafter 1D), the second blocking structure (141) is oriented lengthwise along a second direction (141 extending lengthwise in a second direction shown in annotated Fig 4A/4B of Chuang ‘963), and the second direction (second direction shown in annotated Fig 4A/4B of Chuang ‘963, hereinafter 2D) is different than the first direction (1D)(annotated Fig 4A/4B of Chuang ‘963 discloses 2D is different than 1D); and
wherein the first blocking structure (140) and the second blocking structure (141) are formed of a first material (Para [0020] discloses 140 and 141 comprised of polysilicon), the first isolation structure (50) and the second isolation structure (51) are formed of a second material (isolation structures (50 and 51) disclosed as silicon oxide in Para [0015]), and the first material is different than the second material (silicon oxide)(polysilicon of 140 and 141 being different than silicon oxide of 50 and 51).
With respect to Claim 2 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, but Chuang ‘963 fails to explicitly disclose wherein:
the first material has a first reflectivity;
the second material has a second reflectivity; and
the first reflectivity is less than the second reflectivity.
Nevertheless, Chuang ‘963 teaches the first material (polysilicon of 140 and 141 as described above) and the second material (silicon oxide of 50 and 51 as described above). Examiner notes that these are the same materials disclosed for the first material of the blocking structures and second material of the isolation structure as disclosed in Para [0019 and 0021] of the instant application.
Therefore the polysilicon of Chuang ‘963 and the silicon dioxide of Chuang ‘963 must behave the same as the polysilicon and silicon dioxide of the instant application and so the first reflectivity of the first material (polysilicon) is less than the second reflectivity of the second material (silicon dioxide). A person of ordinary skill in the art would recognize the interchangeability of the first material (polysilicon of Chuang ‘963) and the second material (silicon dioxide of Chuang ‘963) shown in the prior art for the corresponding elements disclosed in the specification. Caterpillar Inc. v. Deere & Co., 224 F.3d 1374, 56 USPQ2d 1305 (Fed. Cir. 2000)
As incorporated, the first material (polysilicon) has a first reflectivity (reflectivity of polysilicon); the second material (silicon dioxide) has a second reflectivity (reflectivity of silicon dioxide); and the first reflectivity is less than the second reflectivity as described above.
With respect to Claim 7 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, and Chuang ‘963 further discloses wherein:
the third sub-portion (3SP) is between the second sub-portion (2SP) and the fourth sub-portion (4SP);
the second sub-portion (2SP), the third sub-portion (3SP), and the fourth sub-portion (4SP) are oriented lengthwise along the first direction (1D) (annotated Fig 4A/4B of Chuang ‘963 discloses 2SP, 3SP and 4SP oriented lengthwise along 1D); and
the second sub-portion (2SP) and the fourth sub-portion (4SP) have a first length (first length of 2SP and 4SP as shown in annotated Fig 4A/4B of Chuang ‘963, hereinafter FL) along the first direction (1D), the third sub-portion (3SP) has a second length (second length of 2SP and 4SP as shown in annotated Fig 4A/4B of Chuang ‘963, hereinafter SL) along the first direction (1D), and the second length (SL) is different than the first length (FL)(annotated Fig 4A/4B of Chuang ‘963 discloses first length is different than the second length in the first direction).
With respect to Claim 9 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, and Chuang ‘963 further discloses wherein the second sub-portion (2SP), the third sub-portion (3SP), and the fourth sub-portion (4SP) are doped the same (annotated Fig 4A/4B of Chuang ‘963 discloses 2SP, 3SP and 4SP as portions of region 90 which Para [0016] discloses as doped with a P-type dopant, therefore as all three regions are parts of the larger region 90, they are doped the same).
With respect to Claim 10 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, and Chuang ‘963 further discloses wherein the first sub-portion (1SP) is doped differently than the second sub-portion (2SP), the third sub-portion (3SP), and the fourth sub-portion (SP) (Para [0016] discloses region 80, of which 1SP is a part as shown in annotated Fig 4A of Chuang ‘963 has n-type dopant and annotated Fig 4A/4B of Chuang ‘963 discloses 2SP, 3SP and 4SP as portions of region 90 which Para [0016] discloses as doped with a P-type dopant, therefore 1SP is doped differently than 2SP, 3SP and 4SP).
With respect to Claim 14 Chuang ‘963 discloses a semiconductor device (Fig 1-4B) comprising:
a shallow trench isolation structure (50, Fig 4A, Para [0015]) disposed over a semiconductor substrate (45, Fig 4A, Para [0014]);
a first sub-portion (first sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 1SP) and a second sub-portion of a portion (second sub-portion shown in annotated Fig 4A/4B of Chuang ‘963, Para [0016], hereinafter 2SP) of in the semiconductor substrate (45), wherein the shallow trench isolation structure (50) circumscribes (50 circumscribing 1SP (1SP is within structure 50 as shown in annotated Fig 4A/4B) disclosed in annotated Fig 4A/4B of Chuang ‘963) the first sub-portion (1SP) and the first sub-portion (1SP) circumscribes (annotated Fig 4A/4B of Chuang ‘963 discloses 1SP circumscribes 2SP) the second sub-portion (2SP); and
a blocking structure (140, Fig 4A, Para [0018]) disposed over (Fig 4A discloses 140 over structure 50) the shallow trench isolation structure (50), wherein the blocking structure (140) surrounds (annotated Fig 4A/4B of Chuang ‘963 discloses 140 surrounds 1SP as 1SP is within structure 140) the first sub-portion (1SP) and the blocking structure (140) includes at least one blocking feature disposed along each side of the first sub-portion (1SP)(annotated Fig 4A/4B of Chuang ‘963 discloses a structure 140 along each side (left side and right side) of 1SP).
With respect to Claim 15 Chuang ‘963 discloses all limitations of the semiconductor device of claim 14, and Chuang ‘963 further discloses wherein the shallow trench isolation structure (50) is a first shallow trench isolation structure (Fig 4A discloses multiple shallow trench isolation structures) and the semiconductor device further includes a second shallow trench isolation structure (51, Fig 4A, Para [0015]), wherein the second shallow trench isolation structure (51) circumscribes (annotated Fig 4A/4B of Chuang ‘963 discloses 51 circumscribes 2SP) the second sub-portion (2SP) and the first sub-portion (1SP) circumscribes (annotated Fig 4A/4B of Chuang ‘963 discloses 1SP circumscribes structure 51) the second shallow trench isolation structure (51).
With respect to Claim 18 Chuang ‘963 discloses all limitations of the semiconductor device of claim 14, and Chuang ‘963 further discloses wherein a width (a width of 140 as shown in annotated Fig 4A of Chuang ‘963) of the blocking structure (140) is at least 30% of a width (a width of 50 as shown in annotated Fig 4A of Chuang ‘963) of the shallow trench isolation structure (50) (annotated Fig 7A/7B_2 of Chuang ‘369 discloses a width of 140 and a fourth width of 50. The cited limitations do not limit the beginning and ending points of the widths. There exists, then, a width of 140 of 3Å and a width of 50 of 4Å, therefore the width of 140 is at least 30% of the width of 50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-6 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘963 in view of Chuang et al. (US 2010/0001369 A1, hereinafter Chuang ‘369), in view of the following arguments.
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With respect to Claim 3 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, but Chuang ‘963 fails to explicitly disclose wherein:
a first width of the first blocking structure is along the second direction and a second width of the second blocking structure is along the first direction; the first blocking structure is disposed on a first portion of the first isolation structure, wherein the first portion of the first isolation structure has a third width along the second direction and the first width is at least 30% of the third width; and the second blocking structure is disposed on a second portion of the first isolation structure, wherein the second portion of the second isolation structure has a fourth width along the first direction and the second width is at least 30% of the fourth width.
Nevertheless, in a related endeavor (Fig 7A-7B of Chuang ‘369), Chuang ‘369 teaches
a first width (width of first 700 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) of the first blocking structure (first 700 as shown in annotated Fig 7A/7B_2 of Chuang ‘369, Para [0039], hereinafter 1BF) is along the second direction (second direction as shown in annotated Fig 7A/7B_2 of Chuang ‘369) and a second width (width of second 700 as shown in annotated Fig 7A/7B _2 of Chuang ‘369) of the second blocking structure (second 700 as shown in annotated Fig 7A/7B_2 of Chuang ‘369, Para [0039], hereinafter 2BF) is along the first direction (first direction as shown in annotated Fig 7A/7B_2 of Chuang ‘369);
the first blocking structure (1BF) is disposed on a first portion (first portion of 142 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) of the first isolation structure (142, Fig 7B of Chuang ‘369, Para [0039]), wherein the first portion (first portion of 142 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) of the first isolation structure (142) has a third width (third width of first portion of 142 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) along the second direction (second direction as shown in annotated Fig 7A/7B_2 of Chuang ‘369) and the first width (width of first 700 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) is at least 30% of the third width (third width of first portion of 142 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) (annotated Fig 7A/7B_2 of Chuang ‘369 discloses a first width and a third width. The cited limitations do not limit the beginning and ending points of the widths. There exists, then, a first width of 700 of 3Å and a third width of 142 of 4Å, therefore the first width is at least 30% of the third width); and
the second blocking structure (2BF) is disposed on a second portion (second portion of 142 as shown in annotated Fig 7A/7B_2 of Chuang ‘369) of the first isolation structure (142), wherein the second portion (second portion of 2BF as shown in annotated Fig 7A/7B_2 of Chuang ‘369) of the second isolation structure (2BF) has a fourth width (fourth width of 2BF as shown in annotated Fig 7A/7B_2 of Chuang ‘369) along the first direction (first direction as shown in annotated Fig 7A/7B_2 of Chuang ‘369) and the second width (width of second 700 as shown in annotated Fig 7A/7B _2 of Chuang ‘369) is at least 30% of the fourth width (fourth width of 2BF as shown in annotated Fig 7A/7B_2 of Chuang ‘369) (annotated Fig 7A/7B_2 of Chuang ‘369 discloses a second width and a fourth width. The cited limitations do not limit the beginning and ending points of the widths. There exists, then, a second width of 700 of 3Å and a fourth width of 2BF of 4Å, therefore the second width is at least 30% of the fourth width).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s teaching of a first width of the first blocking structure is along the second direction and a second width of the second blocking structure is along the first direction; the first blocking structure is disposed on a first portion of the first isolation structure, wherein the first portion of the first isolation structure has a third width along the second direction and the first width is at least 30% of the third width; and the second blocking structure is disposed on a second portion of the first isolation structure, wherein the second portion of the second isolation structure has a fourth width along the first direction and the second width is at least 30% of the fourth width into Chuang ‘963’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, because as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the shapes of the blocking structures (1BF and 2BF) and their widths and the width of the isolation structures (as taught by Chuang ‘369) would be used as the blocking structures and their widths in (140 and 141) and the widths of isolation structures (50 and 51) of Chuang ‘963.
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With respect to Claim 4 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, and Chuang ‘963 further discloses wherein:
the first sub-portion (1SP) has a first dimension (annotated Fig 4A/4B of Chuang ‘963 shows 1SP having a first dimension) along the first direction (1D) and a second dimension (annotated Fig 4A/4B of Chuang ‘963 shows 1SP having a second dimension) along the second direction (2D);
But Chuang ‘963 fails to explicitly disclose the first blocking structure includes a first blocking feature and a second blocking feature oriented lengthwise along the first direction, wherein the first blocking feature and the second blocking feature are separated by a spacing along the first direction; and
a sum of the spacing, a first length of the first blocking feature along the first direction, and a second length of the second blocking feature along the first direction is less than the first dimension of the first sub-portion along the first direction.
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Nevertheless, in a related endeavor (Fig 7A-7B of Chuang ‘369), Chuang ‘369 teaches the first blocking structure (second 700 from left, Fig 7A and 7B of Chuang ‘369, Para [0039]) includes a first blocking feature (first 700 as shown in annotated Fig 7A of Chuang ‘369, hereinafter 1BF) and a second blocking feature (second 700 as shown in annotated Fig 7A of Chuang ‘369, Para [0039], hereinafter 2BF) oriented lengthwise along the first direction (first direction as shown in annotated Fig 7A of Chuang ‘369)(1BF and 2BF oriented lengthwise along first direction shown in annotated Fig 7A of Chuang ‘369), wherein the first blocking feature (1BF) and the second blocking feature (2BF) are separated by a spacing (spacing as disclosed in annotated Fig 7A of Chuang ‘369, hereinafter spacing) along the first direction (first direction as shown in annotated Fig 7A of Chuang ‘369); and a sum of the spacing, a first length (first length of 1BF shown in annotated Fig 7A of Chuang ‘369) of the first blocking feature (1BF) along the first direction (first direction as shown in annotated Fig 7A of Chuang ‘369), and a second length (second length of 2BF shown in annotated Fig 7A of Chuang ‘369) of the second blocking feature (2BF) along the first direction (first direction as shown in annotated Fig 7A of Chuang ‘369) is less than the first dimension (first dimension of 134) of the first sub-portion (134, Fig 7B of Chuang ‘369, Para [0021]) along the first direction (first direction as shown in annotated Fig 7A of Chuang ‘369)(annotated Fig 7A of Chuang ‘369 discloses sum of spacing and first length of 1BF and second length of 2BF, along first direction is less than first dimension of 134 in first direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s teaching of the first blocking structure includes a first blocking feature and a second blocking feature oriented lengthwise along the first direction, wherein the first blocking feature and the second blocking feature are separated by a spacing along the first direction; and a sum of the spacing, a first length of the first blocking feature along the first direction, and a second length of the second blocking feature along the first direction is less than the first dimension of the first sub-portion along the first direction into Chuang ‘963’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, because as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the shapes of the blocking structures (1BF and 2BF), their spacings and their lengths as taught by Chuang ‘369 and the first dimension of the first sub portion would be used as the blocking structures, their spacings and their lengths in (140 and 141) and the first dimension of the first sub portion (1SP) of Chuang ‘963.
With respect to Claim 5 Chuang ‘963 as modified by Chuang ‘369 discloses all limitations of the semiconductor device of claim 4, and Chuang ‘369 further discloses wherein:
the spacing (spacing) is a first spacing (disclosed in annotated Fig 7A of Chuang ‘369);
the second blocking structure (second 700 from left, Fig 7A and 7B of Chuang ‘369, Para [0039]) includes a third blocking feature (third 700 as shown in annotated Fig 7A of Chuang ‘369, hereinafter 3BF) and a fourth blocking feature (fourth 700 as shown in annotated Fig 7A of Chuang ‘369, hereinafter 4BF) oriented lengthwise along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369), wherein the third blocking feature (BF) and the fourth blocking feature (4BF) are separated by a second spacing (second spacing as disclosed in annotated Fig 7A of Chuang ‘369, hereinafter second spacing) along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369); and
a sum of the second spacing (second spacing), a third length (third length of 3BF shown in annotated Fig 7A of Chuang ‘369) of the third blocking feature (3BF) along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369), and a fourth length (fourth length of 4BF shown in annotated Fig 7A of Chuang ‘369) of the fourth blocking feature (4BF) along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369) is less than the second dimension (second dimension of 134) of the first sub-portion (134, Fig 7B of Chuang ‘369, Para [0021]) along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369)(annotated Fig 7A of Chuang ‘369 discloses sum of second spacing and third length of 3BF and fourth length of 4BF along second direction is less than the second dimension of 134 along the second direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s further teaching of the spacing is a first spacing; the second blocking structure includes a third blocking feature and a fourth blocking feature oriented lengthwise along the second direction, wherein the third blocking feature and the fourth blocking feature are separated by a second spacing along the second direction; and a sum of the second spacing, a third length of the third blocking feature along the second direction, and a fourth length of the fourth blocking feature along the second direction is less than the second dimension of the first sub-portion along the second direction into Chuang ‘963 as modified by Chuang ‘369’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 as modified by Chuang ‘369 in the manner set forth above, at least, because as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the spacings and lengths of the blocking features and second dimension of the first sub-portion as taught by Chuang ‘369 would be used as the blocking structures, their spacings and their lengths in (140 and 141) and the second dimension of the first sub portion (1SP) along the second direction of Chuang ‘963 as modified by Chuang ‘369.
With respect to Claim 6 Chuang ‘963 as modified by Chuang ‘369 discloses all limitations of the semiconductor device of claim 5, and in an embodiment (Para [0039] of Chuang ‘369 discloses an embodiment wherein the pillars are rectangular) Chuang ‘369 further teaches wherein:
the first blocking feature (1BF) and the second blocking (2BF) feature have a first width along the second direction (first width of 1BF and 2BF shown in annotated Fig 7A of Chuang ‘369); and
the third blocking feature (3BF) and the fourth blocking feature (4BF) have a second width along the second direction (second width of 3BF and 4BF shown in annotated Fig 7A of Chuang ‘369), wherein the second width is different than the first width (The cited limitations do not limit the beginning and ending points of the widths. There exists, then, a second width of 3BF and 4BF of 3Å and a first width of 1BF and 2BF of 4Å, therefore the second width is different than the first width).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s further teaching of the first blocking feature and the second blocking feature have a first width along the second direction; and the third blocking feature and the fourth blocking feature have a second width along the second direction, wherein the second width is different than the first width into Chuang ‘963 as modified by Chuang ‘369’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 as modified by Chuang ‘369 in the manner set forth above, at least, as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the widths of the blocking features as taught by Chuang ‘369 would be used as the widths of the blocking features, (140 and 141) in the device of Chuang ‘963 as modified by Chuang ‘369.
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With respect to Claim 16 Chuang ‘963 discloses all limitations of the semiconductor device of claim 14, and Chuang ‘963 further discloses wherein:
the first sub-portion (1SP) has a first side (first side disclosed on annotated Fig 4B of Chuang ‘963, hereinafter 1S), a second side (second side disclosed on annotated Fig 4B of Chuang ‘963, hereinafter 2S), a third side (third side disclosed on annotated Fig 4B of Chuang ‘963, hereinafter 3S), and a fourth side (fourth side disclosed on annotated Fig 4B of Chuang ‘963, hereinafter 4S), wherein the first side (1S) and the second side (2S) extend lengthwise along a first direction (first direction shown in annotated Fig 4B of Chuang ‘963, hereinafter 1D)(1S and 2S extending lengthwise along 1D shown in annotated Fig 4B of Chuang ‘963), the third side (3S) and the fourth side (4S) extend lengthwise along a second direction (second direction shown in annotated Fig 4B of Chuang ‘963, hereinafter 2D) (3S and 4S extending lengthwise along 2D shown in annotated Fig 4B of Chuang ‘963), and the second direction (2D) is different than the first direction (1D)(annotated Fig 4B of Chuang ‘963 discloses 2D is different than 1D);
But Chuang ‘963 fails to explicitly disclose a first blocking feature is disposed on the shallow trench isolation structure along the first side of the first sub-portion, a second blocking feature is disposed on the shallow trench isolation structure along the second side of the first sub-portion, a third blocking feature is disposed on the shallow trench isolation structure along the third side of the first sub-portion, and a fourth blocking feature is disposed on the shallow trench isolation structure along the fourth side of the first sub-portion; and
the first blocking feature and the second blocking feature are oriented lengthwise along the first direction and the third blocking feature and the fourth blocking feature are oriented lengthwise along the second direction.
Nevertheless, in a related endeavor (Fig 7A-7B of Chuang ‘369), Chuang ‘369 teaches a first blocking feature (first 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 1BF) is disposed on (Fig 7B and Para [0039] of Chuang ‘369 discloses 700 over 142) the shallow trench isolation structure (142, Fig 7B of Chuang ‘369, Para [0039]) along the first side (left side as shown in Fig 7B of Chuang ‘369) of the first sub-portion (134, Fig 7B of Chuang ‘369, Para [0021]), a second blocking feature (second 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 2BF) is disposed on the shallow trench isolation structure (142)(Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the second side (right side as shown in Fig 7B of Chuang ‘369) of the first sub-portion (134), a third blocking feature (third 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 3BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the third side (top side of 134 as shown in annotated Fig 7A/7B_3 of Chuang ‘369) of the first sub-portion (134), and a fourth blocking feature (fourth 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 4BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the fourth side (bottom side of 134 as shown in annotated Fig 7A/7B_3 of Chuang ‘369) of the first sub-portion (134); and
the first blocking feature (1BF) and the second blocking feature (2BF) are oriented lengthwise along the first direction (first direction as shown in annotated Fig 7A/7B_3 of Chuang ‘369)(1BF and 2BF oriented lengthwise along first direction shown in annotated Fig 7A of Chuang ‘369) and the third blocking feature (3BF) and the fourth blocking feature (4BF) are oriented lengthwise along the second direction (second direction as shown in annotated Fig 7A of Chuang ‘369)(3BF and 4BF oriented lengthwise along first direction shown in annotated Fig 7A/7B_3of Chuang ‘369).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s teaching of a first blocking feature is disposed on the shallow trench isolation structure along the first side of the first sub-portion, a second blocking feature is disposed on the shallow trench isolation structure along the second side of the first sub-portion, a third blocking feature is disposed on the shallow trench isolation structure along the third side of the first sub-portion, and a fourth blocking feature is disposed on the shallow trench isolation structure along the fourth side of the first sub-portion; and the first blocking feature and the second blocking feature are oriented lengthwise along the first direction and the third blocking feature and the fourth blocking feature are oriented lengthwise along the second direction into Chuang ‘963’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the dispositions of the first, second, third and fourth blocking features on the sub-portions and shallow trench isolations as taught by Chuang ‘369 would be used as the dispositions of the blocking features (1BF and 2BF) on the sub-portions and shallow trench isolations and also 3BF and 4F of Chuang ‘369 would all be used in the device of Chuang ‘963.
With respect to Claim 17 Chuang ‘963 as modified by Chuang ‘369 discloses all limitations of the semiconductor device of claim 16, and Chuang ‘369 discloses further wherein:
a fifth blocking feature (fifth 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 5BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the first side (left side as shown in Fig 7B of Chuang ‘369) of the first sub-portion (134), a sixth blocking feature (sixth 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 6BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the second side (right side as shown in Fig 7B of Chuang ‘369) of the first sub-portion (134), a seventh blocking feature (seventh 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 7BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the third side (top side of 134 as shown in annotated Fig 7A/7B_3 of Chuang ‘369) of the first sub- portion (134), and an eighth blocking feature (eighth 700 as shown in annotated Fig 7A/7B_3 of Chuang ‘369, Para [0039], hereinafter 8BF) is disposed on the shallow trench isolation structure (142) (Fig 7B of Chuang ‘369 discloses blocking features 700 disposed on (above) 142) along the fourth side (bottom side of 134 as shown in annotated Fig 7A/7B_3 of Chuang ‘369) of the first sub-portion (142); and
the fifth blocking feature (5BF) and the sixth blocking feature (6BF) are oriented lengthwise along the first direction (first direction as shown in annotated Fig 7A/7B_3 of Chuang ‘369)(annotated Fig 7A/7B_3 of Chuang ‘369 discloses 5BF and 6BF oriented lengthwise along first direction) and the seventh blocking feature (7BF) and the eighth blocking feature (8BF) are oriented lengthwise along the second direction (second direction as shown in annotated Fig 7B of Chuang ‘369) (annotated Fig 7A/7B_3 of Chuang ‘369 discloses 7BF and 8BF oriented lengthwise along second direction).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Chuang ‘369’s further teaching of a fifth blocking feature is disposed on the shallow trench isolation structure along the first side of the first sub-portion, a sixth blocking feature is disposed on the shallow trench isolation structure along the second side of the first sub-portion, a seventh blocking feature is disposed on the shallow trench isolation structure along the third side of the first sub- portion, and an eighth blocking feature is disposed on the shallow trench isolation structure along the fourth side of the first sub-portion; and the fifth blocking feature and the sixth blocking feature are oriented lengthwise along the first direction and the seventh blocking feature and the eighth blocking feature are oriented lengthwise along the second direction into Chuang ‘963 as modified by Chuang ‘369’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches that the inactive regions as individual devices. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, as Chuang ‘369 teaches in Para [0039] the use of individual devices can protect the doped regions and dielectric regions during any polishing process.
As incorporated, the dispositions of the fifth, sixth, seventh and eighth blocking features on the sub-portions and shallow trench isolations as taught by Chuang ‘369 would be used as fifth, sixth, seventh and eighth blocking features with the orientations taught by Chang ‘369 in the device of Chuang ‘963 as modified by Chaung ‘369.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘963 in view of Mehrotra (US 2012/0104540 A1, hereinafter Mehrotra ‘540), in view of the following arguments.
With respect to Claim 8 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, but Chuang ‘963 fails to explicitly disclose wherein the first isolation structure has a first depth into the semiconductor substrate, the second isolation structure has a second depth into the semiconductor substrate, and the first depth is greater than the second depth.
Nonetheless, in a related endeavor (Fig 2A-2H of Mehrotra ‘540), Mehrotra ‘540 teaches wherein the first isolation structure (2112, Fig 2F of Mehrotra ‘540, Para [0025]) has a first depth (depth of 2112 as disclosed in Fig 2F of Mehrotra ‘540, Para [0025]) into the semiconductor substrate (2002, Fig 2B of Mehrotra ‘540, Para [0021]), the second isolation structure (2529, Fig 2F of Mehrotra ‘540, Para [0025]) has a second depth (depth of 2529 as disclosed in Fig 2F of Mehrotra ‘540, Para [0025]) into the semiconductor substrate (2002), and the first depth (depth of 2112) is greater than the second depth (depth of 2529)(depth of 2112 is greater than depth of 2529 as disclosed in Fig 2F of Mehrotra ‘540 and Para [0025]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Mehrotra ‘540’s teaching of the first isolation structure has a first depth into the semiconductor substrate, the second isolation structure has a second depth into the semiconductor substrate, and the first depth is greater than the second depth into Chuang ‘963’s device. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, because , as Mehrotra ‘540 teaches in Para [0004] using the deeper trenches provides protection from adjacent higher voltage regions.
As incorporated, the depth of the second isolation structures being greater than the depth of the first isolation structure as taught by Mehrotra ‘540 would be used as the depths of the first and second isolation structures (50 and 51) of Chuang ‘963.
Claims 11-13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘963 in view of Ema et al. (US 2005/0227440 A1, hereinafter Ema ‘440), in view of the following arguments.
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With respect to Claim 11 Chuang ‘963 discloses all limitations of the semiconductor device of claim 1, but Chuang ‘963 fails to explicitly disclose wherein: a patterned photoresist mask has a first dimension along the first direction and a second dimension along the second direction, wherein the patterned photoresist mask is used during an implantation process when fabricating the semiconductor device; and a length of the first blocking structure along the first direction is at least 50% of the first dimension of the patterned photoresist mask along the first direction.
Nevertheless, in a related endeavor (Fig 1A-12 of Ema ‘440), Ema ‘440 teaches a patterned photoresist mask (PR2, Fig 3E of Ema ‘440) has a first dimension (first dimension of PR2, Fig 1B of Ema ‘440 discloses a top view of the SRAM device of Fig 3A-3L, Para [0107 and 0108] and PR2 runs on top of gate structures of 3E and therefore on 1B so it has a first dimension along the first direction) along the first direction (first direction as shown in annotated Fig 3E of Ema ‘440) and a second dimension (second dimension of PR2 as shown in in annotated Fig 3E of Ema ‘440) along the second direction (second direction as shown in annotated Fig 3E of Ema ‘440), wherein the patterned photoresist mask (PR2) is used during an implantation process when fabricating the semiconductor device (Examiner note, the limitation, “is used during an implantation process when fabricating the semiconductor device” is functional language in a device claim, nonetheless PR2 used during an implantation when fabricating the device is disclosed in Fig 3E and Para [0113] of Ema ‘440); and
a length (length of Rp) of the first blocking structure (Rp, Fig 3D and 3E of Ema ‘440, Para [0112]) along the first direction (first direction as shown in annotated Fig 3E of Ema ‘440) is at least 50% of the first dimension (first dimension of PR2. Fig 1B of Ema ‘440 discloses a top view of the SRAM device of Fig 3A-3L, Para [0107 and 0108], therefore to cover the regions of the device as shown in Fig 3E and disclosed in Para [0113], PR2 has a dimension in the first direction) of the patterned photoresist mask (PR2) along the first direction (first direction as shown in annotated Fig 3E of Ema ‘440) (Fig 1B and 3E of Ema ‘440 discloses a length of Rp along the first direction and a first dimension of the patterned photoresist. The cited limitations do not limit the beginning and ending points of the widths. There exists, then, a length of Rp of 3 Å and a dimension of PR2 of 4Å, therefore the length is at least 50% of the first dimension).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ema ‘440’s teaching of a patterned photoresist mask has a first dimension along the first direction and a second dimension along the second direction, wherein the patterned photoresist mask is used during an implantation process when fabricating the semiconductor device; and a length of the first blocking structure along the first direction is at least 50% of the first dimension of the patterned photoresist mask along the first direction into Chuang ‘963’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘963 also is also open to photoresist structures as it discloses the use of lithographic processes to create the features but does not provide specific details. Ema ‘440 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches the use of photoresist structures. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, because Ema ‘440 provides the person of ordinary skill in the art the details of the lithographic processes disclosed by Chuang ‘963 so Ema ‘440 would reduce the R&D time that would be needed to develop these processes.
As incorporated, the patterned photoresist mask (PR2), it’s dimension and the lengths of the first blocking structure (Rp) of Ema ‘440 would be used as the patterned photoresist mask in the device of Chuang ‘963.
With respect to Claim 12 Chuang ‘963 as modified by Ema ‘440 discloses all limitations of the semiconductor device of claim 11, and Ema ‘440 further teaches wherein a length (length of Gn as shown in annotated Fig 3E of Ema ‘440) of the second blocking structure (Gn, as shown in annotated Fig 3E of Ema ‘440, Para [0112]) along the second direction (second direction as shown in annotated Fig 3E of Ema ‘440) is at least 50% of the second dimension (second dimension of PR2 as shown in in annotated Fig 3E of Ema ‘440) of the patterned photoresist mask (PR2) along the second direction (second direction as shown in annotated Fig 3E of Ema ‘440) (annotated 3E of Ema ‘440 discloses a length of Gn along the second direction and a second dimension of PR2 along the second direction. The cited limitations do not limit the beginning and ending points of the length and dimension. There exists, then, a length of Gn of 3 Å and a dimension of PR2 of 4Å, therefore the length is at least 50% of the second dimension).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ema ‘440’s further teaching of a length of the second blocking structure along the second direction is at least 50% of the second dimension of the patterned photoresist mask along the second direction into Chuang ‘963 as modified by Ema ‘440’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘963 also is also open to photoresist structures as it discloses the use of lithographic processes to create the features but does not provide specific details. Ema ‘440 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches the use of photoresist structures. The ordinary artisan would have been motivated to modify Chuang ‘963 as modified by Ema ‘440 in the manner set forth above, at least, because Ema ‘440 provides the person of ordinary skill in the art the details of the lithographic processes disclosed by Chuang ‘963 so Ema ‘440 would reduce the R&D time that would be needed to develop these processes.
As incorporated, the length of the second blocking structure along the second direction and the second dimension of the photoresist mask along the second direction would be used in the device of Chuang ‘963 as modified by Ema ‘440.
With respect to Claim 13 Chuang ‘963 as modified by Ema ‘440 discloses all limitations of the semiconductor device of claim 11, and Chuang ‘963 as modified by Ema ‘440 discloses further wherein the patterned photoresist mask (PR2 as incorporated into Chuang ‘963 described above) includes more than one photoresist feature (Fig 3E of Ema ‘440 discloses a photoresist feature over Rp and a second photoresist feature over gates Gp on the right side of the structure of Fig 3E).
With respect to Claim 19 Chuang ‘963 discloses all limitations of the semiconductor device of claim 14, but Chuang ‘963 fails to explicitly disclose wherein a length of the blocking structure is at least 50% of a length of a patterned photoresist feature that covers the second sub-portion during an implantation process used during fabrication of the semiconductor device.
Nevertheless, in a related endeavor (Fig 1A-12 of Ema ‘440), Ema ‘440 teaches wherein a length (length of Rp as shown in annotated Fig 3E of Ema ‘440) of the blocking structure (Rp, as shown in annotated Fig 3E of Ema ‘440, Para [0112]) is at least 50% of a length (a length of PR3) of a patterned photoresist feature (PR2, Fig 3E of Ema ‘440, Para [0112]) (annotated 3F of Ema ‘440 discloses a length of Rp and a length of PR3. The cited limitations do not limit the beginning and ending points of the length and dimension. There exists, then, a length of Rp of 3 Å and a length of PR2 of 4Å, therefore the length of Rp is at least 50% of a length of PR3) that covers the second sub-portion (second sub portion disclosed in annotated Fig 3F of Ema ‘440) during an implantation process used during fabrication of the semiconductor device (Examiner note, the limitation, “during an implantation process used during fabrication of the semiconductor device” is functional language in a device claim, nonetheless PR2 used during an implantation when fabricating the device is disclosed in Fig 3F and Para [0114] of Ema ‘440).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ema ‘440’s further teaching of a length of the blocking structure is at least 50% of a length of a patterned photoresist feature that covers the second sub-portion during an implantation process used during fabrication of the semiconductor device Chuang ‘963’s device. Chuang ‘963 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘963 also is also open to photoresist structures as it discloses the use of lithographic processes to create the features but does not provide specific details. Ema ‘440 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches the use of photoresist structures. The ordinary artisan would have been motivated to modify Chuang ‘963 in the manner set forth above, at least, because Ema ‘440 provides the person of ordinary skill in the art the details of the lithographic processes disclosed by Chuang ‘963 so Ema ‘440 would reduce the R&D time that would be needed to develop these processes.
As incorporated, the length of the second blocking structure along the second direction and the second dimension of the photoresist mask along the second direction would be used in the device of Chuang ‘963.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chuang ‘369 in view of Ema ‘440, in view of the following arguments.
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With respect to Claim 20 Chuang ‘369 discloses a semiconductor device (Fig 5A-6B) comprising:
a doped region (136, Fig 5B, Para [0021]) of a semiconductor substrate (106, Fig 5B, Para [0018]) disposed between a first isolation structure (140, Fig 5B, Para [0022]) and a second isolation structure (142, Fig 5B, Para [0022]), wherein the first isolation structure (140) surrounds the doped region (136)(140 surrounding 136 disclosed in Fig 5A) and the doped region (136) surrounds the second isolation structure (142)(136 surrounding 142 disclosed in Fig 5A)
a blocking structure (502, Fig 5B, Para [0029]) disposed over the first isolation structure (140)(502 over 140 disclosed in Fig 5B) and configured to surround the doped region (136)(Fig 5A discloses 140 surrounding 136 and Para [0035] discloses polishing stop structure 502 as a “ring-type structure having a rectangular shape”), wherein the blocking structure (502) includes a first set of blocking structures (first set disclosed in annotated Fig 5A/5B of Chuang ‘369, hereinafter 1BS) oriented lengthwise along a first direction (orientation along first direction disclosed in annotated Fig 5A/5B of Chuang ‘369) and a second set of blocking structures (second set disclosed in annotated Fig 5A/5B of Chuang ‘369, hereinafter 2BS) oriented lengthwise along a second direction (orientation along second direction disclosed in annotated Fig 5A/5B of Chuang ‘369) that is different than the first direction (disclosed in annotated Fig 5A/5B of Chuang ‘369); and
wherein a portion (portion of 1BS as disclosed in annotated Fig 5A/5B of Chuang '369) of the first set of blocking structures (1BS) is disposed along a side (top side) of the doped region (136) circumscribed by the doped region (136)(136 circumscribing inner 502 disclosed in annotated Fig 5A/5B of Chuang '369) and used during fabrication of the semiconductor device (Examiner note, the limitation, “and used during fabrication of the semiconductor device” is functional language in a device claim, nonetheless inner 502 is disclosed as polishing stopper for the device, Para [0036]),
But Chuang ‘369 fails to explicitly disclose a patterned photoresist feature wherein the patterned photoresist feature is oriented lengthwise along the first direction.
Nevertheless, in a related endeavor (Fig 1A-12 of Ema ‘440), Ema ‘440 teaches a patterned photoresist feature (PR2, Fig 3E of Ema ‘440, Para [0113]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ema ‘440’s teaching of a patterned photoresist feature wherein the patterned photoresist feature is oriented lengthwise along the first direction into Chuang ‘369’s device. Chuang ‘369 teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate. Chuang ‘369 is also open to photoresist structures as it discloses the use of lithographic processes to create the features but does not provide specific details. Ema ‘440 also teaches a device layout for a semiconductor device with inactive regions over doped regions and dielectric regions in a substrate and further teaches the use of photoresist structures. The ordinary artisan would have been motivated to modify Chuang ‘369 in the manner set forth above, at least, because Ema ‘440 provides the person of ordinary skill in the art the details of the lithographic processes disclosed by Chuang ‘369, so incorporating teachings from Ema ‘440 would reduce the R&D time that would be needed to develop these processes.
As incorporated, the patterned photoresist feature and its orientation along the first direction as taught by Ema ‘440 would be incorporated as a patterned photoresist feature orientated lengthwise along the first direction in the device is Chuang ‘369.
Chuang ‘369 as modified by Ema ‘440 discloses and a sum of lengths of the portion (portion of 1BS) of the first set of blocking structures (1BS) is at least 50% of a length of a patterned photoresist feature (a length of PR2) (The cited limitations do not limit the beginning and ending points of the lengths of the blocking structures and the photoresist. There exists, then, a length of the portions of 1BS of 2Å and a length of PR2, as incorporated above of 3Å, therefore the sum of the lengths of the portion of 1BS is at least 50% of the length of PR2), wherein the patterned photoresist feature (PR2) is oriented lengthwise along the first direction (1BS is orientated lengthwise along the first direction, therefore PR2 of Ema ‘440 as incorporated above is also oriented lengthwise along the first direction).
Conclusion
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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