DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/18/2025 has been entered.
Response to Amendment
Applicant’s amendment filed on 12/18/2025 is acknowledged. Claims 1, 11, 21 have been amended.
Response to Arguments
Applicant’s arguments with respect to claims 1-15, 21-25 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 21-22, 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US 2020/0135580 A1) in view of Sandhu (US 7235459 B2).
Regarding claim 1, Hsieh teaches a semiconductor device structure (device in Figs. 2-14 of Hsieh), comprising:
a first fin (241) extending from a substrate (substrate on which the fins are formed as described in [0029] of Hsieh), wherein the first fin comprises a first portion (S/D portion of fin 241, shown in Fig. 12) including a first sidewall (left sidewall of 241);
a second fin (240) extending from the substrate adjacent the first fin, wherein the second fin comprises a second portion (S/D portion of fin 240) including a second sidewall (right sidewall of 240) facing the first sidewall;
an insulating material (270 as labeled in Fig. 4 of Hsieh) disposed between the first and second fins;
a third fin (231) extending from the substrate adjacent the second fin, wherein the third fin comprises a third portion (S/D portion of fin 231);
a first source/drain epitaxial feature (portion of 740 attached to fin 241 in Fig. 13) extending from the first portion;
a second source/drain epitaxial feature (portion of 740 attached to fin 240 in Fig. 13) extending from the second portion, wherein the first source/drain epitaxial feature is merged with the second source/drain epitaxial feature (as shown in Fig. 13);
a third source/drain epitaxial feature (731 in Fig. 13) extending from the third substrate portion;
a dielectric material (portion of 275 between fins 241 and 240, as shown in Fig. 11) positioned over the insulating material (as implied in Fig. 4 of Hsieh, the layer 275 is formed over the insulating material, so this limitation is satisfied) at a first distance (distance from this portion of 275 to the left sidewall of fin 241) away from a first plane (plane of left sidewall of fin 241) defined by the first sidewall and a second distance (distance from this liner portion 275 to the right sidewall of fin 240) away from a second plane (plane of right sidewall of fin 240) defined by the second sidewall, wherein the first distance is substantially the same as the second distance (both first and second distances are the same as the thickness of the spacer layer 270), and wherein the merged first and second source/drain epitaxial features is disposed over the dielectric material (as shown in Fig. 13 of Hsieh); and
a dielectric feature (the dielectric feature comprising of 275-400-410-500 between fins 231 and 240 in Fig. 13-14) disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature.
But Hsieh is silent as in teaching that the insulating material extending from the first fin to the second fin (it is not explicit whether the insulating material 270 of Hsieh covers the portion of the top surface of the substrate 102 in Fig. 1 of Hsieh that extends from the first fin to the second fin).
Sandhu teaches a method of forming an isolation structure between fins (Figs. 1-7 of Sandhu). The isolation structure comprises an insulating material (oxide layer 26 in Fig. 3) extending from the first fin to the second fin (see Fig. 3 of Sandhu); a dielectric material (34 in Fig. 4) disposed over the insulating material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the insulating material 270 of Hsieh as disclosed by Sandhu in order to simplify the manufacturing process since Sandhu is a simple blanket deposition process.
Regarding claim 2, Hsieh in view of Sandhu teaches all limitations of the semiconductor device structure of claim 1, and also teaches wherein the dielectric feature comprises:
a liner (275 in Fig. 13);
a low-K dielectric material (410 are low-k dielectric material, as stated in [0042]) disposed on the liner; and
a high-K dielectric material (500 is a high-k material, as stated in [0045] of Hsieh) disposed on the second liner and the low-K dielectric material.
Regarding claim 21, Hsieh teaches a semiconductor device structure (device in Figs. 2-14 of Hsieh), comprising:
a first substrate portion (fin 241);
a firsts source/drain epitaxial feature (portion of 740 attached to fin 241 in Fig. 13) disposed over the first substrate portion;
a second substrate portion (fin 240);
a second source/drain epitaxial feature (portion of 740 attached to fin 240 in Fig. 13) disposed over the second substrate portion and adjacent the first source/drain epitaxial feature, wherein the first source/drain epitaxial feature is merged with the second source/drain epitaxial feature (as shown in Fig. 13);
an insulating material (270, as shown in Fig. 4) disposed between the first and second substrate portions; and
a dielectric material (portion of 275 between fins 241 and 240, as shown in Fig. 4) comprising a first portion (portion of 275 between fins 241 and 240 in the S/D region, as shown in Figs. 10-13) and a second portion (portion of 275 between fins 240 and 241 under the gate region 800, as shown in Fig. 14), wherein the first portion of the dielectric material is disposed over the insulating material (as implied in Fig. 4 of Hsieh, the layer 275 is formed over the insulating material, so this limitation is satisfied) and below the merged first and second source/drain epitaxial features (as shown in Fig. 13 of Hsieh).
But Hsieh is silent as in teaching that the insulating material extending from the first substrate portion to the second substrate portion.
Sandhu teaches a method of forming an isolation structure between fins (Figs. 1-7 of Sandhu). The isolation structure comprises an insulating material (oxide layer 26 in Fig. 3) extending from the first fin to the second fin (see Fig. 3 of Sandhu); a dielectric material (34 in Fig. 4) disposed over the insulating material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the insulating material 270 of Hsieh as disclosed by Sandhu in order to simplify the manufacturing process since Sandhu is a simple blanket deposition process.
Regarding claim 22, Hsieh in view of Sandhu teaches all limitations of the semiconductor device structure of claim 21, and further comprising a gate electrode layer disposed around the second portion of the dielectric material (as defined in claim 21 above and shown in Fig. 14 of Hsieh).
Regarding claim 24, Hsieh in view of Sandhu teaches all limitations of the semiconductor device structure of claim 22, and further comprising a dielectric feature (275 to 500 between fins 231 and 240 in Figs. 10-14 of Hsieh) disposed adjacent the second source/drain epitaxial feature (as shown in Fig. 13).
Regarding claim 25, Hsieh in view of Sandhu teaches all limitations of the semiconductor device structure of claim 24, and also teaches wherein the dielectric feature is disposed adjacent the gate electrode layer (as shown in Fig. 14 of Hsieh).
Claims 3-5, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Sandhu as applied to claim 2 above, and further in view of Ching et al. (US 2020/0119004 A1).
Regarding claim 3, Hsieh in view of Sandhu teaches all limitations of the semiconductor device structure of claim 2, but does not teach the semiconductor device further comprising: a first plurality of semiconductor layers disposed over the first portion; a second plurality of semiconductor layers disposed over the second portion; and a third plurality of semiconductor layers disposed over the third portion.
Ching teaches a semiconductor device (Figs. 12A-12C of Ching) where a plurality of semiconductor layers is disposed over a fin portion on a substrate (see Fig. 12C); and a metal gate electrode (1208 in Fig. 12A) surrounding each of the plurality of semiconductor layers; source/drain epitaxial features (1102-1104) adjacent to the metal gate electrode.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of semiconductor layers (nanowire channels), as disclosed by Ching, in order to increase gate-channel interface area.
As incorporated, there is a plurality of semiconductor layers on each fin, as shown in Figs. 10-14 of Hsieh and Figs. 12A-12C of Ching.
Regarding claim 4, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 3, and also teaches wherein the dielectric feature is disposed between the second plurality of semiconductor layers and the third plurality of semiconductor layers (as combined in claim 3 above).
Regarding claim 5, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 4, and further comprising: a first gate electrode layer (portion of gate 800 surrounding fins 241 and 240 in Fig. 14 of Hsieh, with the top portion of the fins replaced by the stack of nanowire channel, as combined from Ching above) surrounding the first and second pluralities of semiconductor layers; and a second gate electrode layer (portion of gate 800 surrounding the fin 231) surrounding the third plurality of semiconductor layers.
Regarding claim 8, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 3, and also teaches wherein the dielectric material comprises a first portion (portion of 275 in the S/D region, which is shown in Fig. 13 of Hsieh) and a second portion (portion of 275 in the channel region, which is shown in Fig. 14 of Hsieh), wherein the merged first and second source/drain epitaxial features is disposed over the first portion of the dielectric material (as shown in Fig. 13 of Hsieh), and the second portion of the dielectric material is disposed between the first plurality of semiconductor layers and the second plurality of semiconductor layers (as shown in Fig. 14 of Hsieh and combined in claim 3 above).
Regarding claim 9, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 8, and also teaches wherein the first portion of the dielectric material has a first width (width of 275 at the base level of the fins 241, 240, as shown in Fig. 13 of Hsieh), and the second portion of the dielectric material has a second width (width of 275 at the interface with the gate 800 in Fig. 14 of Hsieh) greater than the first width (as shown in Fig. 13-14 of Hsieh, the width of 275 at the gate interface is greater than that at the base of fins).
Regarding claim 10, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 3, and also teaches wherein the dielectric material is not between (the term “between” covers a broad range of situations, including a first situation where the dielectric material is at the middle of two stacks of nanowires but not at same height level; or a second situation where the dielectric material is at the middle of two stacks of nanowires and also at same height level. In this claim, the term is restricted to the situation where it is at the same level. As such, this is satisfied by Hsieh and Ching) the first and second pluralities of semiconductor layers.
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in view of Sandhu and Ching.
Regarding claim 11, Hsieh teaches a semiconductor device structure (device in Figs. 2-14 of Hsieh), comprising:
a first fin (240) extending from a substrate, wherein the first fin comprises a first portion (portion of fin 240 not surrounded by gate 800 in Fig. 14);
a second fin (241) extending from the substrate adjacent the first fin, wherein the second fin comprises a second portion (portion of fin 241 not surrounded by gate 800 in Fig. 14);
an insulating material (270 as labeled in Fig. 4 of Hsieh) disposed between the first and second fins;
a third fin (242) extending from the substrate adjacent the second fin, wherein the third fin comprises a third portion (portion of fin 242 not surrounded by gate 800 in Fig. 14);
a first source/drain epitaxial feature (portion of 740 attached to fin 240 in Fig. 13) adjacent the first plurality of semiconductor layers;
a second source/drain epitaxial feature (portion of 740 attached to fin 241 in Fig. 13) adjacent the second plurality of semiconductor layers, wherein the first source/drain epitaxial feature is merged with the second source/drain epitaxial feature (as shown in Fig. 13 of Hsieh);
a third source/drain epitaxial feature (731) adjacent the third plurality of semiconductor layers;
a first dielectric layer (portion of 275 between fins 240 and 241, as shown in Fig. 11-13) comprising a first portion (portion of 275 between fins 241 and 240 that is overlapped by the gate 800) and a second portion (portion of 275 between fins 241 and 240 that is in the S/D region) disposed over the insulating material (as implied in Fig. 4 of Hsieh, the layer 275 is formed over the insulating material, so this limitation is satisfied), wherein the first portion of the first dielectric layer has a first width (width of 275), and the second portion is disposed below the merged first and second source/drain epitaxial features (as shown in Fig. 13 of Hsieh); and
a dielectric feature (the dielectric feature comprising of 275-400-410-500 in Fig. 13-14 between fins 241 and 242), wherein the dielectric feature has a second width greater than the first width (see Fig. 13-14 of Hsieh).
But Hsieh does not teach that the first fin comprises a first plurality of semiconductor layers disposed over the first portion; the second fin comprises a second plurality of semiconductor layers disposed over the second portion; the insulating material extending from the first fin to the second fin; the third fin comprises a third plurality of semiconductor layers disposed over the third portion; the first portion of the first dielectric layer is disposed between the first plurality of semiconductor layers and the second plurality of semiconductor layers; the dielectric feature is disposed between the second plurality of semiconductor layers and the third plurality of semiconductor layers.
Sandhu teaches a method of forming an isolation structure between fins (Figs. 1-7 of Sandhu). The isolation structure comprises an insulating material (oxide layer 26 in Fig. 3) extending from the first fin to the second fin (see Fig. 3 of Sandhu); a dielectric material (34 in Fig. 4) disposed over the insulating material.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the insulating material 270 of Hsieh as disclosed by Sandhu in order to simplify the manufacturing process since Sandhu is a simple blanket deposition process.
But Hsieh in view of Sandhu does not teach that the first fin comprises a first plurality of semiconductor layers disposed over the first portion; the second fin comprises a second plurality of semiconductor layers disposed over the second portion; the third fin comprises a third plurality of semiconductor layers disposed over the third portion; the first portion of the first dielectric layer is disposed between the first plurality of semiconductor layers and the second plurality of semiconductor layers; the dielectric feature is disposed between the second plurality of semiconductor layers and the third plurality of semiconductor layers.
Ching teaches a semiconductor device (Figs. 12A-12C of Ching) where a plurality of semiconductor layers is disposed over a fin portion on a substrate (see Fig. 12C); and a metal gate electrode (1208 in Fig. 12A) surrounding each of the plurality of semiconductor layers; source/drain epitaxial features (1102-1104) adjacent to the metal gate electrode.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the plurality of semiconductor layers (nanowire channels), as disclosed by Ching, in order to increase gate-channel interface area.
As incorporated, the portion of each of first, second and third fins overlapped by the gate electrode is replaced with a plurality of semiconductor layers, as shown in Figs. 10-14 of Hsieh and Figs. 12A-12C of Ching. Moreover, the dielectric feature (275-500 in Figs. 13-14 of Hsieh) is disposed between the second plurality of semiconductor layers and the third plurality of semiconductor layers (over the fins 241 and 242, respectively).
Regarding claim 12, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 11, and also teaches wherein the dielectric feature comprises:
a second dielectric layer (275 in Fig. 14 of Hsieh);
a low-K dielectric material (410 are low-k dielectric material, as stated in [0042] of Hsieh) disposed on the second dielectric layer; and
discrete high-K dielectric materials (500 is a high-k material, as stated in [0045] of Hsieh) disposed on the second dielectric layer and the low- K dielectric material.
Regarding claim 13, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 12, and also teaches wherein each discrete high-K dielectric material has a U shape with respect to a cross-sectional view of the semiconductor device structure (see Fig. 14 of Hsieh).
Regarding claim 14, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 13, and further comprising a gate electrode layer (800 in Fig. 14 of Hsieh) surrounding the first, second, and third pluralities of semiconductor layers.
Regarding claim 15, Hsieh-Sandhu-Ching teaches all limitations of the semiconductor device structure of claim 11, and also teaches wherein the second portion of the first dielectric layer has a third width (portion of layer 275 at the base of fins 240/241 in Fig. 13 of Hsieh) less than the first width of the first portion of the first dielectric layer.
Allowable Subject Matter
Claims 6-7, and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art of record does not disclose or fairly suggest a semiconductor device structure satisfying “wherein the high-K dielectric material comprises: a first portion disposed between the second source/drain epitaxial feature and the third source/drain epitaxial feature; and a second portion disposed between the first gate electrode layer and the second gate electrode layer” along with other limitations of claims 1-2.
Regarding claim 23, the prior art of record does not disclose or fairly suggest a semiconductor device structure satisfying “wherein the first portion of the dielectric material has a height less than a height of the second portion of the dielectric material” along with other limitations of the semiconductor device structure of claim 22.
The closest prior art of record are Hsieh et al. (US 2020/0135580 A1).
Hsieh teaches most of the limitations of the claims with the dielectric feature identified to be the stack of 275 to 500 in Figs. 13-14 of Hsieh, where the layer 500 is a high-k material. However, this high-k material is removed completely in the source/drain region so there is no portion of the high-k dielectric material between the source/drain epitaxial features of the adjacent fins.
Conclusion
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/Tuan A Hoang/Primary Examiner, Art Unit 2898