DETAILED ACTION
Claims 1-27 are pending.
Claims 21-25 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of prior-filed applications under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on November 24, 2025, is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 17/562,003 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
The examiner notes that applicant has cited NPL without providing relevant page numbers. While the NPL has been considered, please cite relevant page numbers for any NPL cited in the future, as required by 37 CFR 1.98(b)(5), to ensure consideration thereof.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
In paragraphs 1-3, applicant lists related applications. Patent numbers must be inserted for any application that has resulted in a patent. While none of the applications appear to have been patented at the time of drafting this Office Action, this note will serve as a reminder, until allowance of this application, to insert patent numbers as related applications issue.
The disclosure is objected to because of the following informalities:
In paragraphs 9-10, 36, 44, 50, 56, 58, 67, 71, 74, 79, 83, and 90, applicant discloses the action/verb of tagging is contained in the control words. How is a verb in a control word? This appears to be grammatically incorrect and the examiner suggests replacing “the tagging” with --the precedence information--.
In paragraph 37, “yet to loaded” is grammatically incorrect and must be reworded.
For any other paragraph that includes language similar to that pointed out in the claim objections below, please amend the paragraphs similarly to the claims.
Appropriate correction is required.
Claim Objections
Claim 1 is objected to because of the following informalities:
In line 1, replace “processing comprising:” with --processing, the method comprising:-- so that the steps are explicitly tied to the method and not potentially to the parallel processing.
In lines 7-8, applicant claims that the tagging is contained in the control words. Tagging is a verb and, thus, it is grammatically incorrect to say that a verb is contained in an encoded control word. It appears that “the tagging” should be replaced with --the precedence information--.
In claim 1, line 9, it appears that either “provided” should be replaced with
--performed--, or “tagging” should be replaced with --precedence information--.
Multiple times in claim 1, applicant refers to “independent loops”. The examiner questions whether “independent” is appropriate. This could be interpreted as the loops have nothing to do with one another. However, paragraph 68 clearly sets forth dependencies/interaction between the loops (e.g. one loop generates data consumed by another loop). If applicant is trying to claim different/separate loops, then the examiner recommends using --separate-- instead of “independent”.
Claims 26-27 are objected to similar reasoning as claim 1, apart from the first claim 1 objection.
Claim 27 is further objected to because --and-- needs to be inserted at the end of line 2.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 2, “logic” for determining a precedence value based on the precedence information. The examiner has been unable to find sufficient structure disclosed in the specification for performing this determining. Paragraphs 22, 29, and 36, among others, state that generic hardware can derive a precedence value. Generic hardware is not sufficient structure. Paragraph 36 also states that compute elements within the 2D array can derive the value. However, a compute element is understood to be a type of generic processor and deriving a precedence value is not a deemed a coextensive function (MPEP 2181(II)(B)). Thus, disclosure of a processor+algorithm would be required, and such is absent. As such, broadest reasonable interpretation (BRI) is taken and 112(a)/(b) rejections appear below.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 2, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the logic to perform the claimed function. The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 and 26-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claims 1 and 26-27, the term “wide” is a relative term which renders the claims indefinite. The term is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Specifically, the examiner is not clear on where the line is drawn between wide and not wide. For purposes of prior art examination, anything larger than 1 bit will be deemed wide. The examine recommends deletion of “wide”.
Regarding claim 2, the claimed logic+function limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as described above, the written description fails to disclose the corresponding structure(s), material(s), or act(s) for performing the entire claimed function(s) and to clearly link the structure(s), material(s), or act(s) to the function(s). Therefore, the claim(s) are indefinite and are rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim(s) so that the claim limitation(s) will no longer be interpreted as a limitation(s) under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure(s), material(s), or act(s) perform the entire claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure(s), material(s), or act(s) disclosed therein to the function(s) recited in the claim(s), without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure(s), material(s), or act(s) and clearly links them to the function(s) so that one of ordinary skill in the art would recognize what structure(s), material(s), or act(s) perform the claimed function(s), applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure(s), material(s), or act(s) for performing the claimed function(s) and clearly links or associates the structure(s), material(s), or act(s) to the claimed function(s), without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure(s), material(s), or act(s), which are implicitly or inherently set forth in the written description of the specification, perform the claimed function(s). For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 5 and 9 are indefinite because it is unclear whether the claims are requiring the presence of both loads and stores, or if the “or” in claim 1 means that only one of the types needs to exist. Applicant could replace “and” with --and/or-- in claims 5 and 9, or establish the presence of both at the beginning of claims 5 and 9. The examiner will interpret claims 5 and 9 to include “and/or” for purposes of prior art examination.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 18, “each computing element completing”. Is this referring to each computing element in the at least one grouping, or to all computing elements in the array? The examiner assumes the former, but this must be made clear.
In claim 20, “the grouping”. From parent claim 17, there is at least one grouping.
Claims 2-20 are rejected due to their dependence on an indefinite claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Swanson et al. (“WaveScalar”), in view of Etsion et al. (US 2021/0334106).
Referring to claim 1, Swanson has taught a processor-implemented method for parallel processing comprising:
accessing a two-dimensional (2D) array of compute elements (FIG.3 and FIG.5(c)), wherein each compute element within the array of compute elements is known to a compiler (see section 5.1 and section 3. An executable is compiled for the WaveScalar array processor. Thus, the processing elements in the array are known to a compiler.) and is coupled to its neighboring compute elements within the array of compute elements (see FIG.5(c) and note the connections between processing elements (represented by squares). Connections are reconfigurable and can vary in order to execute the specific compiled algorithm. This means that any two neighboring elements are connected to one another (though that connection may not be used for a given algorithm));
providing control for the compute elements on a cycle-by-cycle basis (from FIG.5(c), over a number of cycles, the array of elements is controlled to carry out the mapped algorithm), wherein control is enabled by a stream of wide control words generated by the compiler (the multi-bit (wide) control words are sent to the elements to carry out the compiled algorithm. More than one bit is required to implement more than two operations (and more than two operations are shown in FIGs.5(a)-(c));
tagging memory access operations with precedence information (see FIG.2 and the “Memory ordering” section on pages 4-5. Each memory operation is tagged with a link of the form <predecessor, this, successor>), wherein the tagging is contained in the control words (the link is in the control words since it is passed with the memory access operations at run-time), wherein the tagging is for loop operations (FIG.5 shows a loop executing on the array and the tagged link used for memory operations in the loop (see FIG.5(b)), and wherein the tagging is provided by the compiler at compile time (again, see the “Memory ordering” sections on pages 4-5 (2nd paragraph, in particular));
Swanson has not taught loading control word data for multiple, independent loops into the compute elements. Instead, Swanson loads for a single loop as shown in FIG.5. However, Etsion has taught concurrently executing different dataflow graphs in the same array (see the abstract). Such would allow increased utilization of the array, which includes 2000 processing elements (Swanson, section 4, 1st paragraph). That is, the loop of FIG.5 only consumes a small subset of elements (e.g. 23, per FIG.5(c)). If the rest of the array is left unused, then its full processing potential is not being realized. Thus, per Etsion, multiple tasks can be sent to different portions of the array concurrently to increase parallelism and throughput. Just as FIG.5 of Swanson shows a task with a loop, any other task could similarly include a loop with memory access operations so as to efficiently repeat processing (including memory access) where desired. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Swanson to load control word data for a second, independent loop into the compute elements.
Swanson, as modified, has taught executing the multiple, independent loops (again, multiple loops sent to the array would be executed); and accessing memory based on the precedence information (see section 4. The memory accesses occur in the order indicated by the precedence information (tag information)), wherein the memory access includes loads and/or stores for data relating to the independent loops (as loops are repeatedly executed, multiple loads and stores therein will be performed. For instance, in the loop of FIG.5, there is a load and a store, which are repeatedly executed for as many iterations as the loop requires. Thus, there are loads and stores across iterations).
Referring to claim 2, Swanson, as modified, has taught the method of claim 1 wherein a precedence value is determined by logic, based on the precedence information (see the first full paragraph on page 5. To ensure a gap does not exist, a value among the tag information is determined to compare against an expected value, e.g. “M’s succ number matches the sequence number of its next operation”).
Referring to claim 3, Swanson, as modified, has taught the method of claim 1 wherein the precedence information comprises a template value supplied by the compiler (see FIG.2 and the aforementioned “Memory ordering” section. The precedence information comprises a <pred, this, succ> template, which is filled in by the compiler).
Referring to claim 4, Swanson, as modified, has taught the method of claim 3 wherein the template value includes a seed value (any of pred, this, and succ may be called a seed value. Or, the wave number, which is also attached to each memory operation, may be a seed number (again, see the “Wave numbers” section on page 4, and the “Memory ordering” section (third paragraph)).
Referring to claim 5, Swanson, as modified, has taught the method of claim 1 wherein a precedence value enables hardware ordering of the loads and stores (see the “Memory ordering” section).
Referring to claim 6, Swanson, as modified, has taught the method of claim 1 further comprising establishing a grouping of compute elements within the array of compute elements (see FIG.5. Of all 2000 compute elements, a group of 23 is established to execute the loop. Also, as modified, where the array is configured to execute multiple loops at once, there would be multiple groups of compute elements established, one for each loop).
Referring to claim 7, Swanson, as modified, has taught the method of claim 6 wherein the grouping establishes boundaries for the executing the multiple, independent loops (each group is separate from the next and, thus, has boundaries. For instance, in FIG.5(c), the group assigned instructions has a boundary. Another group would have another boundary).
Referring to claim 8, Swanson, as modified, has taught the method of claim 6 further comprising establishing a precedence pointer for the grouping (each memory operation has a pointer to a memory location (“address” on page 5, first full paragraph). This may be referred to as a precedence pointer in a system that gives precedence to some memory operations over others).
Claim 26 is mostly rejected for similar reasoning as claim 1. Further, Swanson has taught a computer program product embodied in a non-transitory computer readable medium for parallel processing, the computer program product comprising code which causes one or more processors to perform the claimed operations (a compiler is software code, which must be stored on a non-transitory medium to execute. This code causes all of the claimed steps to be performed, either during compiling or at run-time when the compiled code needs to be executed).
Claim 27 is rejected for similar reasoning as claim 26, where the system would comprise a memory to store compiler instructions that cause claimed actions to occur when executed by a processor.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Swanson in view of Etsion and Oskin et al. (US 2005/0166205).
Referring to claim 9, Swanson, as modified, has taught the method of claim 6 but has not taught establishing a precedence pointer for the grouping (from claim 8), wherein the precedence pointer indicates actual hardware progress of the loads and stores (from claim 9). However, Oskin has taught more implementation details for the same WaveScalar architecture (note similar figures between the two documents, shared inventors, etc.). In Oskin’s FIG.10, an ordering implementation is shown with various pointers to indicate progress for memory operations. The pointers include “oldest issued”, “last issued”, expected next”, and pointers to entries in the order table to read their information. One or more of these precedence pointers helps determine when progress has been made on previous loads/stores. For instance, LD <4, 7, 8> will be allowed to proceed when, for example, the prior instruction ST <3, 4, ?> has issued such that the “last issued” pointer is set to 4. Since this implementation is intended for the same system as Swanson, and because it is one way to implement the checks at the end of the first full paragraph on page 5 to realize desired ordering of memory operations, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Swanson to establish a precedence pointer for the grouping, wherein the precedence pointer indicates actual hardware progress of the loads and stores.
Referring to claim 10, Swanson, as modified, has taught the method of claim 6 but has not taught establishing a precedence pointer for the grouping (from claim 8), wherein a store operation is cleared from an access buffer when the precedence pointer is greater than a precedence value of the store operation and all load operations with lower precedence values have completed (from claim 10). However, the establishing is obvious for reasoning given in the rejection of claim 9. With this modification, recall that memory operations occur in order. Thus, they are cleared in order in FIG.10 of Oskins. The store instruction ST <3, 4, ?> is cleared from the access buffer (ordering table) (denoted by hatching on the instruction) when the precedence pointer no longer points to the ST instruction in the ordering table (in FIG.10, a precedent pointer points to LD <4, 7, 8>. Thus, the precedence pointer has advanced beyond the store (it is greater than a precedent pointer value for the store) and all prior load operations with lower precedence values (“this” values in their tagged information) have completed, because, again, operations have to be issued in order.
Claims 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over Swanson in view of Etsion and the examiner’s taking of Official Notice.
Referring to claim 11, Swanson, as modified has taught the method of claim 6 but has not taught identifying load hazards and store hazards by comparing load and store addresses to contents of an access buffer. However, recall that multiple separate graphs can be scheduled to the array at the same time. Official Notice is taken that multiple tasks sharing memory space and detection of load/store hazards in that memory space by comparing load/store addresses was well known in the art before applicant’s invention. That is, while a given graph enforces memory ordering, such enforcement is not disclosed between load/stores of different tasks. Thus, in order to allow different tasks to share information with one another and to ensure correct execution, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Swanson to identify load hazards and store hazards by comparing load and store addresses to contents of an access buffer. When a matching address is detected, the system would order the load/store properly so as to ensure one doesn’t execute out of order and access the wrong data.
Referring to claim 12, Swanson, as modified, has taught the method of claim 11 further comprising including a precedence value in the comparing (the load/store addresses that are compared may be called precedence values).
Referring to claim 13, Swanson, as modified, has taught the method of claim 11 further comprising delaying promoting data to a store buffer (from the end of section 4, memory requests go to a store buffer. Thus, there is delay in sending any particular request to the buffer until the execution of the graph reaches the memory request. For instance, in FIG.5(c), there will be a delay in sending store data for the ST instruction until multiple operations before it execute first).
Referring to claim 14, Swanson, as modified, has taught the method of claim 13 wherein the delaying avoids hazards (this is the purpose of the graph building process - to identify dependencies and create a flow that avoids hazards. If the ST executes too early, it may store the wrong value and/or store to the wrong location in memory. Thus, delaying the store is to avoid a hazard).
Referring to claim 15, Swanson, as modified, has taught the method of claim 14 wherein the avoiding hazards is based on a comparative precedence value (the compiler determines the flow based on comparing source/destinations (precedence value) for the instructions. Where matches occur, a dependency may exist, and the graph appropriately reflects the dependency).
Referring to claim 16, Swanson, as modified, has taught the method of claim 14 wherein the hazards include write-after-read, read-after-write, and write-after-write conflicts (all programs being executed must be free of these known hazards to avoid incorrect execution).
Referring to claim 17, Swanson, as modified, has taught the method of claim 6 but has not taught dynamically coupling at least one grouping of compute elements at run time. However, Official Notice is taken that dynamic reconfiguration/coupling of an array was well known in the art before applicant’s invention. Such allows for dynamic adaptation to a current workload. As different asks are required, the array can be reconfigured for those tasks by modifying the couplings to implement each graph for each task. This allows for on-the-fly reconfiguration without stopping the system and reconfiguring it while it is offline, which would add delay. As a result, it would have been obvious to one of ordinary skill in the art before applicant’s invention to modify Swanson to dynamically couple at least one grouping of compute elements at run time.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Swanson in view of Etsion, the examiner’s taking of Official Notice, and Yamada et al. (US 2009/0189686).
Referring to claim 18, Swanson, as modified, has taught the method of claim 17 but has not taught notifying a control unit by each compute element in the at least one grouping of compute elements, based on each compute element completing loop execution. However, Yamada has taught a power control circuit that performs power control for each of multiple cores individually, so that power of a core that has transmitted an interrupt signal indicating process completion notification can be individually turned off (see paragraph 6). Such would allow for power savings for each element in Swanson that is finished with its portion of the loop. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Swanson to notify a control unit by each compute element in the at least one grouping of compute elements, based on each compute element completing loop execution.
Referring to claim 19, Swanson, as modified, has taught the method of claim 18 wherein the notifying indicates loop termination (again, each element is taking part in executing a loop. Thus, when a given element executes the last instruction assigned to it in the loop, that given element indicates its loop termination).
Referring to claim 20, Swanson, as modified, has taught the method of claim 19 further comprising idling each compute element in the grouping of compute elements upon loop termination (in Yamada, the compute elements are turned off, meaning they are idle).
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chen (US 2017/0123795) has taught a CGRA that executes loops and assigns LSIDs to loads/stores, where the LSIDs are ordered for a given iteration. This document is deemed particularly relevant to applicant’s claimed invention.
Smith (US 2018/0032344) has taught a block-based processor, where a compiler assigns LSID to each load and store. The LSID may be within a memory instruction and be related to emission order.
Grafe (US 5,226,131) has taught sequencing instructions in a dataflow computer.
Eggers (US 2006/0179429) has taught building a wavecache
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183