DETAILED ACTION
This Notice is responsive to communication filed on 09/04/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The amendment filed on 9/4/2025 under 37 CFR 1.131(a) has been entered. Claims 1-18 remain pending in the application. Applicant’s amendments to the claims have overcome the 112(b) rejection previously set forth in the Non-Final Office Action mailed 8/14/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "and the fourth lateral surface of the main body is formed by the fourth surface of the first circuit layer and the fourth surface of the second circuit layer." in lines 22-23. There is insufficient antecedent basis for the limitation “the fourth surface” in the claim.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “cuboid body” in claim 14 is used by the claim to mean “having six lateral surfaces,” while the accepted meaning is “having 4 lateral surfaces.” The term is indefinite because the specification does not clearly redefine the term.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim
Claims 10 and 11 are rejected for being dependent on claim 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-5, 8, 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheah (US 20160005718 A1).
Regarding claim 1, as the claim is rejected as indefinite, for the purposes of this rejection, the examiner will interpret “the fourth lateral surface” as a fourth lateral surface of the main body which is also non-coplanar with the first, second, and third lateral surfaces. Cheah teaches a semiconductor interposer device, comprising:
a main body Fig. 1A: 120 (structure) having a first lateral surface, a second lateral surface, and a third lateral surface, wherein the first lateral surface, the second lateral surface, and the third lateral surface are non-coplanar with each other (Fig. 1C annotated below; Fig. 1C shows these surfaces are not coplanar);
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wherein the main body Fig. 1A: 120 comprises:
a first circuit layer Fig. 1A: 122+124 having a first surface, a second surface, a third surface, a fourth surface (annotated Fig. 1C below, top view showing the annotated surfaces of the circuit layer, Fig. 1A shows a cross section view of the different circuit layers), a plurality of first electrical contacts Fig. 1A or Fig. 1C: 104 formed at a first surface of the first circuit layer Fig. 1A: 122+124, and a plurality of second electrical contacts Fig. 1C: 104 formed at a second surface of the first circuit layer Fig. 1A: 122+124; and
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a second circuit layer Fig. 1A: 128 attached to the first circuit layer Fig. 1A: 122+124, wherein the second circuit layer Fig. 1A: 128 has a first surface, a second surface, a third surface, a fourth surface (annotated Fig. 1C, top view showing the annotated surfaces of the circuit layer), a plurality of third electrical contacts Fig. 1C: 104 formed at a first surface of the second circuit layer Fig. 1A: 128, and a plurality of fourth electrical contacts Fig. 1C: 104 formed at a third surface of the second circuit layer Fig. 1A: 128;
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wherein the first circuit layer Fig. 1A: 122+124 is attached to the second circuit layer Fig. 1A: 128 to form the main body Fig. 1A: 120 at a position that the first lateral surface of the main body Fig. 1A: 120 is formed by the first surface of the first circuit layer Fig. 1A: 122+124 and the first surface of the second circuit layer Fig. 1A: 128, the second lateral surface of the main body Fig. 1A: 120 is formed by the second surface of the first circuit layer Fig. 1A: 122+124 and the second surface of the second circuit layer Fig. 1A: 128, the third lateral surface of the main body Fig. 1A: 120 is formed by the third surface of the first circuit layer Fig. 1A: 122+124 and the third surface of the second circuit layer Fig. 1A: 128, and the fourth lateral surface of the main body Fig. 1A: 120 is formed by the fourth surface of the first circuit layer Fig. 1A: 122+124 and the fourth surface of the second circuit layer Fig. 1A: 128, such that the first electrical contacts Fig. 1C: 104 are formed at the first lateral surface of the main body Fig. 1A: 120, the second electrical contacts Fig. 1C: 104 are formed at the second lateral surface of the main body Fig. 1A: 120, the third electrical contacts Fig. 1C: 104 are formed at the first lateral surface of the main body Fig. 1A: 120 and the fourth electrical contacts Fig. 1C: 104 are formed at the third lateral surface of the main body Fig. 1A: 120;
wherein the first electrical contact Fig. 1C: 104 and the second electrical contact Fig. 1C: 104 are electrically connected to each other and the third electrical contact Fig. 1C: 104 and the fourth electrical contact Fig. 1C: 104 are electrically connected to each other (para [0021] connected via backside metal routing Fig. 1A: 138), and the first circuit layer Fig. 1A: 122+124 is not directly electrically connected to the second circuit layer Fig. 1A: 128 through an interface between the first circuit layer Fig. 1A: 122+124 and the second circuit layer Fig. 1A: 128. (Also note that the main body of Cheah could still be applied to claim 1 if the position of the third lateral surface (and third surface) were switched with the position of the fourth lateral surface (and fourth surface)).
Regarding claim 3, Cheah teaches the semiconductor interposer device of claim 1 wherein a normal of the first lateral surface is substantially perpendicular to a normal of the second lateral surface, and wherein the third lateral surface is opposite to the second lateral surface (see annotation below).
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Regarding claim 4, Cheah teaches the semiconductor interposer device of claim 1, wherein a normal of the first lateral surface is substantially perpendicular to a normal of the second lateral surface, and wherein the third lateral surface is opposite to the first lateral surface.
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Regarding claim 5, Cheah teaches the semiconductor interposer device of claim 1 further comprising a third circuit layer Fig. 1A: 130+132, wherein the third circuit layer Fig. 1A: 130+132 has a first surface, a second surface, a third surface, a fourth surface (annotated Fig. 1C, top view showing the annotated surfaces of the circuit layer), a plurality of fifth electrical contacts Fig. 1C: 104 formed at the first surface of the third circuit layer Fig. 1A: 130+132, and a plurality of sixth electrical contacts Fig. 1C: 104 formed at the fourth surface of the third circuit layer Fig. 1A: 130+132, wherein the first lateral surface of the main body Fig. 1A: 120 is formed by the first surface of the first circuit layer Fig. 1A: 122+124, the first surface of the second circuit layer Fig. 1A: 128, and the first surface of the third circuit layer Fig. 1A: 130+132, such that the fifth electrical contacts Fig. 1C: 104 are formed at the first lateral surface of the main body Fig. 1A: 120; wherein the fourth lateral surface of the main body Fig. 1A: 120 is formed by the fourth surface of the first circuit layer Fig. 1A: 122+124, the fourth surface of the second circuit layer Fig. 1A: 128, and the fourth surface of the third circuit layer Fig. 1A: 130+132, such that the sixth electrical contacts Fig. 1C: 104 are formed at the fourth lateral surface of the main body Fig. 1A: 120; wherein the third circuit layer Fig. 1A: 130+132 further comprises a third interconnection layer Fig. 1A/1B: 131+133+136+138+144 integrally extended between the fifth electrical contact Fig. 1C: 104 and the sixth electrical contact Fig. 1C: 104.
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Regarding claim 8, Cheah teaches the semiconductor interposer device of claim 5, wherein the third circuit layer Fig. 1A: 130+132 is attached to and in contact with the first circuit layer Fig. 1A: 122+124 or the second circuit layer Fig. 1A: 128 to form the main body Fig. 1A: 120 (Fig. 1A shows that the third circuit layer Fig. 1A: 130+132 is in contact with the second circuit layer Fig. 1A: 128 at the point of their layers 129 and 131).
Regarding claim 12, Cheah teaches the semiconductor interposer device of claim 1 wherein an electronic component Fig. 1A: 100 is disposed on the first lateral surface, the second lateral surface or the third lateral surface of the main body Fig. 1A: 120 and electrically connected to the first electrical contacts Fig. 1A: 104 on the first lateral surface, the second electrical contacts Fig. 1A: 104 on the second lateral surface, the third electrical contacts Fig. 1A: 104 on the first lateral surface or the fourth electrical contacts Fig. 1A: 104 on the third lateral surface of the main body Fig. 1A: 120 (para [0021]; Fig. 1A, 1B and 1C show the electronic component 100 is connected to the lateral surface via the electrical contacts 104).
Regarding claim 13, Cheah teaches the semiconductor interposer device of claim 1 wherein at least a portion of each of the first electrical contacts Fig. 1A: 104 is protruded out of the first lateral surface of the main body Fig. 1A: 120, wherein at least a portion of each of the second electrical contacts Fig. 1A: 104 is protruded out of the second lateral surface of the main body Fig. 1A: 120, wherein at least a portion of each of the third electrical contacts Fig. 1A: 104 is protruded out of the first lateral surface of the main body Fig. 1A: 120, wherein at least a portion of each of the fourth electrical contacts Fig. 1A: 104 is protruded out of the third lateral surface of the main body Fig. 1A: 120 (Fig. 1A and 1C shows the electrical contacts 104 protruding from the lateral surfaces).
Regarding claim 14, since this claim has been rejected as improper due to the claimed definition of a cuboid having 6 lateral surfaces, The Examiner will interpret the claim as a cuboid body defining four lateral surfaces and 2 non-lateral surfaces, namely the top and bottom surface. Cheah teaches the semiconductor interposer device of claim 1, wherein the main body Fig. 1A: 120 has a cuboid body (para. 0016 “in one embodiment…fabricating 3D cube processors”) defining four lateral surfaces (annotated above) to configure at least the first lateral surface formed by the first surfaces of the first circuit layer Fig. 1A: 122+124 and the second circuit layer Fig. 1A: 128 side-by- side with each other, the second lateral surface formed by the second surfaces of the first circuit layer Fig. 1A: 122+124 and the second circuit layer Fig. 1A: 128 side-by-side with each other, and third lateral surface formed by the third surfaces of the first circuit layer Fig. 1A: 122+124 and the second circuit layer Fig. 1A: 128 side-by-side with each other (see annotation below).
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Using the annotated figures above, the first circuit layer Fig. 1A: 122+124 and the second circuit layer Fig. 1A: 128 as previously defined, it is clear that Cheah teaches a cuboid body where the first surfaces of the first circuit layer and the second circuit layer are side by side as shown in Fig. 1A. Fig. 1C shows the second and third lateral surfaces of the main body which are formed the same as the first lateral surface of the main body.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah (US 20160005718 A1) as applied to claim 1 above, and further in view of Chang (US 20230140683).
Regarding claim 2, although Cheah teaches the substantial features of the claimed invention including the semiconductor interposer device of claim 1, wherein the first circuit layer Fig. 1A: 122+124 is attached to and in contact with the second circuit layer Fig. 1A: 128 to form the main body Fig. 1A: 120, wherein the first circuit layer Fig. 1A: 122+124 further comprises a first interconnection layer Fig. 1A/1B: 123+125+136+138+144 to electrically connect the first electrical contact Fig. 1A/1B: 104 and the second electrical contact Fig. 1A/1C: 104 with each other, wherein the second circuit layer Fig. 1A: 128 further comprises a second interconnection layer Fig. 1A/1B: 129+136+138+144 to electrically connect the third electrical contact Fig. 1A/1C: 104 and the fourth electrical contact Fig. 1A/1C: 104 with each other (Fig. 1A shows that the first and second circuit layers are in indirect contact with each other; para. 0021 teaches the electrical contacts are electrically connected to each other using an interconnection structure including a die backside metal routing 138). But Cheah fails to explicitly teach wherein the interconnection layer extended between the first surface of the first circuit layer and the second surface of the first circuit layer and, wherein the second interconnection layer extended between the first surface of the second circuit layer and the third surface of the second circuit layer. However, Chang teaches (see Fig. 3A/3B) wherein the interconnection layer Fig. 3B: 302b extended between the first surface of the first circuit layer Fig. 3B: 301a and the second surface of the first circuit layer Fig. 3B: 301a and, wherein the second interconnection layer Fig. 3B: 302c extended between the first surface of the second circuit layer Fig. 3B: 301b and the third surface of the second circuit layer Fig. 3B: 301b. Fig. 3A and 3B show the backside metallization layers taught by Chang (para. 0066) that are formed over the entire top surface extending in all lateral directions of the wafers having different dies Fig. 3: 312. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date that the die backside metal routing taught by Cheah be extended from the first surface to the second surface as in Chang’s invention, for the purpose of bonding the wafers (and dies) and ensuring electrical connection (para. 0066).
Regarding claim 6, although Cheah teaches the substantial features of the claimed invention including the semiconductor interposer device of claim 5 wherein the fifth electrical contact Fig. 1C: 104 and the sixth electrical contact Fig. 1C: 104 are electrically connected to each other via the third interconnection layer Fig. 1A/1B: 131+133+136+138+144 (para. 0021 teaches the contacts are connected via backside metal routing Fig. 1A: 138 which is part of the interconnection layer). But Cheah fails to explicitly teach wherein the third interconnection layer is extended between the first surface of the third circuit layer and the fourth surface of the third circuit layer to electrically connect the fifth electrical contact and the sixth electrical contact with each other. However, Chang teaches wherein the third interconnection layer Fig. 3A: backside metallization is extended between the first surface of the third circuit layer Fig. 3A: wafer 1 and the fourth surface of the third circuit layer Fig. 3A: wafer 1 to electrically connect the fifth electrical contact and the sixth electrical contact with each other. Fig. 3A-3B shows a first and second backside metallization layer extended through all the lateral surfaces of the wafer and dies 312; and in para. 0066 Chang teaches that Fig. 3A shows only 3 stacked wafers, but is not limited to 3 (lines 24-27). Chang also teaches the die pads including a plurality of contact pads that are electrically connected to the metal lines (para. 0104). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date that the die backside metal routing taught by Cheah be extended from the first surface to the second surface as in Chang’s invention, for the purpose of bonding the wafers (and dies) and ensuring electrical connection (Chang, para. 0066).
Regarding claim 7, Cheah teaches the semiconductor interposer of claim 6, wherein the first lateral surface is opposite to the fourth lateral surface, and wherein the second lateral surface is opposite to the third lateral surface (annotated below).
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Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cheah (US 20160005718 A1) and Chang (US 20230140683) as applied to claim2 above, and further in view of Guevara et al. (US 20230142680).
Regarding claim 15, although Cheah and Chang teach the substantial features of the claimed invention, they fail to explicitly teach the semiconductor interposer device of claim 2, wherein the first electrical contact is partially embedded in the first surface of the first circuit layer and partially exposed out of the first surface of the first circuit layer, wherein the second electrical contact is partially embedded in the second surface of the first circuit layer and partially exposed out of the second surface of the first circuit layer. However, Guevara teaches the semiconductor interposer device of claim 2, wherein the first electrical contact (see annotated Fig. 3E below) is partially embedded in the first surface (bottom surface of 52) of the first circuit layer Fig. 3E: 52 and partially exposed out of the first surface (bottom surface of 52) of the first circuit layer Fig. 3E: 52, wherein the second electrical contact (annotated below) is partially embedded in the second surface (top surface of 52) of the first circuit layer Fig. 3E: 52 and partially exposed out of the second surface (top surface of 52) of the first circuit layer Fig. 3E: 52. Para. 0030-0033 disclose that the electrical contacts (contact pads) are at least partially embedded in a nonconductive field region at surfaces of the circuit layer 52. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Cheah, Chang and Guevara for the purpose of directly bonding the contact pads without an intervening adhesive and retaining electrical connection (para. 0041, 0044).
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Regarding claim 16, Guevara teaches the semiconductor device of claim 15, wherein the first interconnection layer is integrally extended between an embedded portion of the first electrical contact and an embedded portion of the second electrical contact to electrically connect the first electrical contact and the second electrical contact with each other (see annotated Fig. 3E above regarding first interconnection structure).
Regarding claim 17, Guevara teaches the semiconductor device of claim 16, wherein the third electrical contact is partially embedded in the third surface of the second circuit layer Fig. 3E: 106 and partially exposed out of the third surface of the second circuit layer, wherein the fourth electrical contact is partially embedded in the fourth surface of the second circuit layer Fig. 3E: 106 and partially exposed out of the fourth surface of the second circuit layer (see annotated Fig. 3E above and contact pad parts corresponding to the second circuit layer 106).
Regarding claim 18, Guevara teaches the semiconductor device of claim 17, wherein the second interconnection layer is integrally extended between an embedded portion of the third electrical contact and an embedded portion of the fourth electrical contact to electrically connect the third electrical contact and the fourth electrical contact with each other (see annotated Fig. 3E above and parts corresponding to the second interconnection structure).
Regarding claims 16 and 18, it would have been obvious to one of ordinary skill in the art to combine the teachings of Cheah and Guevara for the purpose of increasing the density of circuitry and double a memory capacity of the stacked device to be used in high bandwidth memory devices or other devices that utilize vertical integration (para. 0046).
Allowable Subject Matter
Claims 9-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 09/04/2025 have been fully considered but they are not persuasive. The current office action describes the aspects of Cheah's invention that teaches the limitations of the amended claims of the present application.
Regarding claim 1, Cheah teaches the electrical contacts formed at all 4 lateral surfaces of the main body 120. Fig. 1B shows the cross-section view of the body with multiple contacts 104 shown on the right side of the figure coupling electronic component 100 to the main body 120. Fig. 1C shows a top view of the whole device including the contacts extending from the lateral surfaces of the device. The mapped portions of the first Fig. 1A: 122+124 and second Fig. 1A: 128 circuit layers show that the circuit layers each have contacts protruding from lateral surfaces. Fig. 1B shows a more in-depth connection of the circuit layers to the contacts.
Regarding claims 5 and 14, Cheah shows in Fig. 1A, that the first surface of the first circuit layer (annotated above) is lined up to the first surface of the second circuit layer (also annotated above) and they form a lateral surface of the main body. Para. 0016 teaches a multi-die (i.e. circuit layer) embodiment of 3D cube processors.
Applicant’s arguments with respect to claims 2, 6, and 15-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 December 4, 2025