DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 8-15, 21-26, is/are rejected under 35 U.S.C. 102(a1) as being anticipated by Agarwal et al., US 2021/0057352 A1.
Claim 8. Agarwal et al., disclose a method (such as the steps from figs. 11-13) comprising: forming a stitching die (item 373: as noted, stitching die refers to a foundation or base die in a package. This die serves as the structural and electrical foundation for other dies in the assembly) by:
-forming a dielectric layer (item 322) over a first substrate layer (item 160);
-forming a first conductive structure (item 316) in the dielectric layer and extending to a first surface of the dielectric layer;
-forming a second conductive structure (item 321) in the dielectric layer and extending to the first surface of the dielectric layer;
-and removing the first substrate layer to expose a second surface of the dielectric layer (this limitation would read through [0046] wherein is disclosed the carrier wafer 160 to be removed without destructively damaging the structures mounted thereon at the time of separation);
-and bonding the stitching die to a first semiconductor die comprising a third conductive structure and to a second semiconductor die comprising a fourth conductive structure, wherein the first conductive structure contacts the third conductive structure and the second conductive structure contacts the fourth conductive structure (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 11. Agarwal et al., disclose the method of claim 8, comprising: forming a first bonding layer over the first semiconductor die and the second semiconductor die; forming a first contact pad in the first bonding layer contacting the third conductive structure; and bonding a second bonding layer of the stitching die to the first bonding layer, wherein: the dielectric layer comprises the second bonding layer (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 12. Agarwal et al., disclose the method of claim 11, wherein forming the dielectric layer of the stitching die comprises: forming an interlayer dielectric layer; forming a passivation layer over the interlayer dielectric layer; and forming the second bonding layer over the passivation layer, wherein the first conductive structure extends through at least a portion of the interlayer dielectric layer, through the passivation layer, and through the second bonding layer (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 13. Agarwal et al., disclose the method of claim 8, comprising: orienting the first semiconductor die in a back side up orientation prior to bonding the stitching die to the first semiconductor die, wherein: the first semiconductor die comprises a second substrate layer, and the third conductive structure extends through the second substrate layer (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 14. Agarwal et al., disclose the method of claim 8, comprising: orienting the first semiconductor die in a top side up orientation prior to bonding the stitching die to the first semiconductor die, wherein: the first semiconductor die comprises a second substrate layer and an interlayer dielectric layer over the second substrate layer, and the third conductive structure extends through the interlayer dielectric layer (this limitation would read through [0055] wherein is disclosed If the warpage produces a bending moment M.sub.3, then the polymer layers 322a, 322b and 322c will have a tendency to warp particularly at the edge 342 in the +z direction and exert positive +z direction forces 352, 353 and 355).
Claim 15. Agarwal et al., disclose the method of claim 8, comprising: orienting the stitching die such that a seal ring (item 345) in the stitching die is laterally offset from a seal ring of the first semiconductor die, as [0041] disclosed the RDL structure 115 and can extend laterally beyond the left and right edges (and those edges not visible) of the chips 105 and 110 as desired).
Claim 21. Agarwal et al., disclose a method (such as the steps from figs. 11-13) comprising: forming a stitching die (item 373: as noted, stitching die refers to a foundation or base die in a package. This die serves as the structural and electrical foundation for other dies in the assembly) by:
-forming a first dielectric layer (item 322) over a first substrate layer (item 160);
-forming a first conductive structure (item 316) in the first dielectric layer and extending to a first surface of the first dielectric layer facing away from the first substrate layer;
-forming a second conductive structure (item 321) in the first dielectric layer and extending to the first surface of the first dielectric layer;
-and removing the first substrate layer; mounting a first semiconductor die and a second semiconductor die to a base (this limitation would read through [0046] wherein is disclosed the carrier wafer 160 to be removed without destructively damaging the structures mounted thereon at the time of separation);
-and bonding the stitching die to the first semiconductor die and the second semiconductor die such that the first surface of the first dielectric layer faces the first semiconductor die and the second semiconductor die and such that the first semiconductor die and the second semiconductor die are between the base and the stitching die (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claims 22-24. Agarwal et al., disclose the method of claim 21, comprising: forming a second dielectric layer between the first semiconductor die and the second semiconductor die prior to bonding the stitching die to the first semiconductor die and the second semiconductor die (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 25. Agarwal et al., disclose the method of claim 21, wherein forming the stitching die comprises: forming a hybrid bonding layer over the first dielectric layer; forming a first conductive pad in the hybrid bonding layer and electrically coupled to the first conductive structure; and forming a second conductive pad in the hybrid bonding layer and electrically coupled to the second conductive structure (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Claim 26. Agarwal et al., disclose the method of claim 25, wherein bonding the stitching die to the first semiconductor die and the second semiconductor die comprises bonding the stitching die to the first semiconductor die and the second semiconductor die such that the first conductive pad is electrically coupled to a third conductive structure of the first semiconductor die and the second conductive pad is electrically coupled to a fourth conductive structure of the second semiconductor die (this limitation would read through [0050] wherein is disclosed the semiconductor chips 105 and 110 are mounted on the RDL structure 115 and secured thereto by way of metallurgical bonds between the interconnects 126 and 128 of the chips 105 and 110 and various of the conductor traces and/or pads 120a of the metallization layer 116d).
Allowable Subject Matter
4. Claims 9-10, 16, 27-28, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 9 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of forming a cooling structure over the second surface of the dielectric layer of the stitching die.
(B) Since claim 10 is dependent claim of objected claim (claim 9), is also objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claim (e.g., claim 9).
(C) Claim 16 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of forming a molding material laterally between the first semiconductor die and the second semiconductor die and laterally adjacent the stitching die; and forming a cooling structure over the molding material to directly contact the second surface of the dielectric layer of the stitching die.
(D) Claim 27 contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of forming a cooling structure over a second surface of the first dielectric layer opposite the first surface.
(F) Since claim 28 is dependent claim of objected claim (claim 27), is also objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claim (e.g., claim 27).
5. Claims 29-31 allowed.
Reasons for Allowance
6. The following is an examiner's statement of reasons for allowance:
7. Regarding claims 29-31, the prior art failed to disclose or reasonably suggest forming a second conductive structure in the first dielectric layer; and removing the first substrate layer; bonding the stitching die to a first semiconductor die; forming a second dielectric layer to surround the stitching die after bonding the stitching die to the first semiconductor die; and forming a cooling structure overlying the stitching die and the second dielectric layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899