Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Analysis for Independent Claims (Dependent Claim Analysis will follow)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (hereinafter Tsai, US 2023/0402278) in view of Lee et al. (hereinafter Lee, US 2016/0197074).
In regards to independent claim 1, Tsai teaches a structure, comprising:
an N-type source/drain epitaxial feature disposed over a substrate (Tsai, Fig. 19, [0018], Item 110a);
a P-type source/drain epitaxial feature disposed over the substrate (Tsai, Fig. 19, [0018], Item 110b);
a first silicide layer disposed directly on the N-type source/drain epitaxial feature (Tsai, Fig. 19, [0037], Item 137a);
a second silicide layer disposed directly on the P-type source/drain epitaxial feature (Tsai, Fig. 19, [0037], Item 137b), wherein the first and second silicide layers comprise a first metal (Tsai, Fig. 19, [0037], Mo),
a third silicide layer disposed directly on the first silicide layer (Tsai, Fig. 19, [0038], Item 139a); and
a fourth silicide layer disposed directly on the second silicide layer (Tsai, Fig. 19, [0038], Item 139b) wherein the third and fourth silicide layer comprise a second metal different from the first metal (Tsai, Fig. 19, [0038], TN),
Tsai fails to explicitly teach the second silicide layer is substantially thicker than the first silicide layer; and the third silicide layer is substantially thicker than the fourth silicide layer.
Lee teaches the second silicide layer is substantially thicker than the first silicide layer; and the third silicide layer is substantially thicker than the fourth silicide layer (Lee, [0077], Fig. 6, “The first metal silicide layer 71 (PMOS) may have a thickness greater than the second metal silicide layer 86 (NMOS). The first metal silicide layer 71 may have the thickness of three to ten times the thickness of second metal silicide layer 86”). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include a thicker silicide for PMOS devices vs NMOS of Lee in order to obtain a contact silicide where the silicide is thicker for PMOS devices. One would have been motivated to make such a combination because it reduces contact resistance for each device.
In regards to independent claim 8, Tsai teaches a method, comprising:
forming an N-type source/drain epitaxial feature over a substrate (Tsai, [0032], “the heavily doped process 132a is performed by implanting an N-type dopant to the first epitaxial layer 110a to further enhance the concentration of the source/drain region for an N-type FinFET device”);
forming a P-type source/drain epitaxial feature over the substrate (Tsai, [0032], “the heavily doped process 132b is performed by implanting an P-type dopant to the second epitaxial layer 110b to further enhance the concentration of the source/drain region for a P-type FinFET device”);
selectively depositing a first silicide layer, wherein the first silicide layer comprises a first portion disposed directly on the N-type source/drain epitaxial feature and a second portion disposed directly on the P-type source/drain epitaxial feature (Tsai, [0034-0037], ALD + Anneal); and
depositing a second silicide layer, wherein the second silicide layer comprises a third portion disposed directly on the first portion of the first silicide layer and a fourth portion disposed directly on the second portion of the first silicide layer (Tsai, [0036-0038], ALD + Anneal).
Tsai fails to explicitly teach wherein the second portion is substantially thicker than the first portion; and wherein the third portion is substantially thicker than the fourth portion.
Lee teaches wherein the second portion is substantially thicker than the first portion; and wherein the third portion is substantially thicker than the fourth portion. (Lee, [0077], Fig. 6, “The first metal silicide layer 71 (PMOS) may have a thickness greater than the second metal silicide layer 86 (NMOS). The first metal silicide layer 71 may have the thickness of three to ten times the thickness of second metal silicide layer 86”). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include a thicker silicide for PMOS devices vs NMOS of Lee in order to obtain a contact silicide where the silicide is thicker for PMOS devices. One would have been motivated to make such a combination because it reduces contact resistance for each device.
In regards to independent claim 14, Tsai teaches a method, comprising:
forming an N-type source/drain epitaxial feature over a substrate (Tsai, [0032], “the heavily doped process 132a is performed by implanting an N-type dopant to the first epitaxial layer 110a to further enhance the concentration of the source/drain region for an N-type FinFET device”);
forming a P-type source/drain epitaxial feature over the substrate (Tsai, [0032], “the heavily doped process 132b is performed by implanting an P-type dopant to the second epitaxial layer 110b to further enhance the concentration of the source/drain region for a P-type FinFET device”);
performing an atomic layer deposition process to simultaneously form a first silicide layer directly on the N-type source/drain epitaxial feature and a second silicide layer directly on the P-type source/drain epitaxial feature, (Tsai, [0034-0037], ALD + Anneal); and
performing a deposition process to simultaneously form a third silicide layer directly on the first silicide layer and a fourth silicide layer directly on the second silicide layer (Tsai, [0036-0038], ALD + Anneal),
Tsai fails to explicitly teach wherein the second silicide layer is substantially thicker than the first silicide layer, wherein the third silicide layer is substantially thicker than the fourth silicide layer.
Lee teaches wherein the second silicide layer is substantially thicker than the first silicide layer, wherein the third silicide layer is substantially thicker than the fourth silicide layer (Lee, [0077], Fig. 6, “The first metal silicide layer 71 (PMOS) may have a thickness greater than the second metal silicide layer 86 (NMOS). The first metal silicide layer 71 may have the thickness of three to ten times the thickness of second metal silicide layer 86”). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include a thicker silicide for PMOS devices vs NMOS of Lee in order to obtain a contact silicide where the silicide is thicker for PMOS devices. One would have been motivated to make such a combination because it reduces contact resistance for each device.
Claim Analysis for Dependent Claims
Claim Objections
Claim 18 is objected to because of the following informalities: claim 18 refers to “the deposition process,” which is interpreted as referring to “the deposition process” of claim 14. However, it could be interpreted as a shorthand for “the atomic layer deposition process” in claim 17. Clarification of the deposition process with a differentiating adjective such as “second” is suggested. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-7, 9-13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Lee.
In regards to dependent claim 2, Tsai teaches wherein the first metal comprises molybdenum (Tsai, [0034]).
In regards to dependent claim 3, Tsai teaches wherein the second metal comprises titanium (Tsai, [0036]).
In regards to dependent claim 4, Tsai teaches wherein the first silicide layer further comprises MoSi (Tsai, [0037]), the second silicide layer further comprises MoSiGe (Tsai, [0038]), the third silicide layer further comprises TiSi (Tsai, [0037] replace Ni with Ti as stated in [0036])), and the fourth silicide layer further comprises TiSiGe (Tsai, [0038]).
In regards to dependent claim 5, Tsai teaches a first nitride layer disposed directly on the third silicide layer; and a second nitride layer disposed directly on the fourth silicide layer, wherein the first and second nitride layers comprise a same material (Tsai, [0041]).
In regards to dependent claim 6, Tsai teaches a first conductive feature disposed directly on the first nitride layer; and a second conductive feature disposed directly on the second nitride layer (Tsai, 148).
In regards to dependent claim 7, Tsai teaches where a total thickness of the first and third silicide layers is substantially the same as a total thickness of the second and fourth silicide layers (Tsai, [0037, 0038]).
In regards to dependent claim 9, Tsai teaches wherein the first silicide layer is deposited at a first process temperature, and the second silicide layer is deposited at a second process temperature substantially greater than the first process temperature (Tsai, [0038, [0040]).
In regards to dependent claim 10, Tsai teaches wherein the first process temperature is less than or equal to about 350 degrees Celsius, and the second process temperature ranges from about 400 degrees Celsius to about 500 degrees Celsius (Tsai, [0038, [0040]).
In regards to dependent claim 11, Tsai teaches depositing a metal layer on the second silicide layer and performing a nitridation process on the metal layer to form a nitride layer (Tsai, [0041]).
In regards to dependent claim 12, Tsai teaches forming conductive features directly on the nitride layer (Tsai, [0042]).
In regards to dependent claim 13, Tsai teaches forming contact openings to expose the N-type source/drain epitaxial feature and the P-type source/drain epitaxial feature, wherein the first silicide layer and the second silicide layer are formed in the contact openings (Tsai, [0033]).
In regards to dependent claim 20, Tsai teaches wherein the third and fourth silicide layers comprise a metal different from a metal of the first and second silicide layers (Tsai, [0037,0038]).
Claim(s) 15-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Lee and Gandikota et al. (hereinafter Gandikota, US 2024/0026529)
In regards to dependent claim 15, Gandikota teaches wherein the atomic layer deposition process comprises: flowing a metal-containing precursor into a processing chamber; and flowing a hydrogen-containing precursor into the processing chamber (Gandikota [0044]). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee and Gandikota before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include the Mo ALD of Gandikota in order to obtain a contact silicide deposited through ALD. One would have been motivated to make such a combination because it creates lower resistivity Molybdenum films
In regards to dependent claim 16, Gandikota teaches the metal-containing precursor comprises MoCl5 (Gandikota [0044]). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee and Gandikota before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include the Mo ALD of Gandikota in order to obtain a contact silicide deposited through ALD. One would have been motivated to make such a combination because it creates lower resistivity Molybdenum films
In regards to dependent claim 17, Gandikota teaches wherein the atomic layer deposition process is performed at a first process temperature (Gandikota [0044]). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee and Gandikota before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include the Mo ALD of Gandikota in order to obtain a contact silicide deposited through ALD. One would have been motivated to make such a combination because it creates lower resistivity Molybdenum films
In regards to dependent claim 18, Lee teaches wherein the deposition process is performed at a second process temperature substantially greater than the first process temperature (Lee, [0140]). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include a thicker silicide for PMOS devices vs NMOS of Lee in order to obtain a contact silicide where the silicide is thicker for PMOS devices. One would have been motivated to make such a combination because it reduces contact resistance for each device.
In regards to dependent claim 19, Gandikota teaches wherein the first process temperature ranges from about 280 degrees Celsius to about 320 degrees Celsius (Gandikota [0044]). It would have been obvious to one of ordinary skill in the art, having the teachings of Tsai and Lee and Gandikota before him before the effective filing date of the claimed invention, to modify the contact silicide taught by Tsai to include the Mo ALD of Gandikota in order to obtain a contact silicide deposited through ALD. One would have been motivated to make such a combination because it creates lower resistivity Molybdenum films
Conclusion
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/WILLIAM C TRAPANESE/Primary Examiner, Art Unit 2812