Office Action Predictor
Application No. 18/196,545

LOW-COST MASK PUNCH FLOW

Non-Final OA §102§103§112
Filed
May 12, 2023
Examiner
RAMALLO, GUSTAVO G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Ndtm Us LLC
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
96%
With Interview

Examiner Intelligence

95%
Career Allow Rate
507 granted / 534 resolved
Without
With
+1.3%
Interview Lift
avg trend
2y 6m
Avg Prosecution
43 pending
577
Total Applications
career history

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.0%
+11.0% vs TC avg
§102
30.2%
-9.8% vs TC avg
§112
15.2%
-24.8% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on April 20, 2023. It is noted, however, that applicant has not filed a certified copy of the PCT/CN/2389449 application as required by 37 CFR 1.55. Election/Restrictions Applicant’s election without traverse of Invention I (claims 1-6 and 12-2) in the reply filed on September 29, 205 is acknowledged. Claims 7-11 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on September 29, 2025. Claim Objections Claims 1-6 and 16-20 are objected to because of the following informalities: Claim 1, lines: 6-10 recites the limitation “the negative photoresists” and “the negative photoresist”. It is believed this is meant to be “the negative photoresist coating”. For purposes of examination this will be interpreted as “the negative photoresist coating” Claim 18, line 1 recites the limitation “the photoresist coating”. It is believed this is meant to be “the negative photoresist coating” . For purposes of examination this will be interpreted as “the negative photoresist coating” Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-6, 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the pillar recesses" in line 10 There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 2 recites the limitation "the pillar recesses" in lines: 1, 4-7, and 9. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 2 recites the limitation "the negative photoresist" in line: 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the negative photoresist coating” Claim 2 recites the limitation "the polymerized photoresist" in line: 8. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the polymerized negative photoresist coating” Claim 3 recites the limitation "the pillar recesses" in lines: 2-3. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 4 recites the limitation "the pillar recesses" in lines: 2 and 4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 4 recites the limitation "the polymerized photoresist" and “any unpolymerized photoresist” in lines: 3-4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the polymerized negative photoresist coating” and “any unpolymerized negative photoresist coating” Claim 5 recites the limitation "the pillar recesses" in lines: 3-4. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 12 recites the limitation "the pillar recesses" and “pillar recesses” in lines: 4-5, 9, and 12 There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 12 recites the limitation "the dummy pillar recesses” in line 14. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the dummy pillar” Claim 12 recites the limitation "the photoresist", “polymerized photoresist”, “the polymerized photoresist”, and “any unpolymerized photoresist” in lines: 8, 10, and 13. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the photoresist coating”, “polymerized photoresist coating”, “the polymerized photoresist coating”, and “any unpolymerized photoresist coating” Claim 15 recites the limitation "the pillar recesses" in line 2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the plurality of pillar recesses” Claim 16 recites the limitation "the plurality of layers" and “the operative pillars” in lines: 1-2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the stack of layers” and “operative pillars” Claim 17 recites the limitation "the plurality of layers" and “the conductive layers” in lines: 1-2. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a plurality of layers” and “the conduction layers” Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 2013/0137266). Claim 1, Chen discloses (Figs. 1-10) a method for fabricating a semiconductor device, comprising: forming (Fig. 3)a plurality of pillar recesses (unlabeled recesses in between 310, 304a and 304b, hereinafter “recesses”) in a semiconductor structure (300, semiconductor workpiece, Para [0017]) comprising a stack of layers (310/312/314, first polysilicon layer/hard mask layer/second polysilicon layer, Para [0017], hereinafter “stack”); applying (Fig. 4) a negative photoresist coating (400, first photoresist layer may be negative photoresist, Para [0018]) over regions containing the plurality of pillar recesses (400 is applied over regions of recesses); exposing (Fig. 5) the negative photoresist coating (400) using a mask (500, first photomask, Para [0019]) to expose the negative photoresist coating (500 has windows 502 which expose 400, Para [0019]) in regions in which dummy pillars (304a/304b, high-aspect features, Para [0017]) are to be formed (304a/304b are within window 502 where 400 is exposed), the exposure causing the negative photoresist coating to polymerize (protons 506 strike 400 in window 502 causing exposed 400 to harden, Para [0019]) and become insoluble to a developer (the hardening makes exposed 400 insoluble to photoresist developer, Para [0019]); and applying (Fig. 6) the developer (unlabeled developing agent, Para [0020], hereinafter “developer”) to the semiconductor structure (developer is applied to 300, Para [0020]) to dissolve the negative photoresist coating in the plurality of pillar recesses that are not exposed (developer dissolves 400 in unexposed portion forming a first opening 600, Para [0020]). Claim 18, Chen discloses (Figs. 1-10) The method of claim 1, wherein the negative photoresist coating comprises a negative photoresist (400 is negative photoresist, Para [0018]). Claim(s) 1 and 17-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2021/0028058). Claim 1, Kim discloses (Figs. 4A-4K) a method for fabricating a semiconductor device, comprising: forming (Fig. 4C) a plurality of pillar recesses (14L, lower holes, Para [0034]) in a semiconductor structure (Fig. 4C is a semiconductor structure as 11 is a semiconductor substrate, Para [0028]) comprising a stack of layers (12/13, dielectric layer/sacrificial layer which will be become conductive layer 19, Para [0029], hereinafter “stack”); applying (Fig. 4F) a negative photoresist coating (11UM is the second mask layer for a negative photoresist which is not labeled, Para [0056], hereinafter “neg”) over regions containing the plurality of pillar recesses (neg would be formed over regions of 14L relabeled as 15L in Fig. 4F); exposing (Fig. 4G) the negative photoresist coating (neg) using a mask (11UM) to expose the negative photoresist coating in regions in which dummy pillars are to be formed (neg is exposed in areas of 15L in Fig. 4G), the exposure causing the negative photoresist coating to polymerize and become insoluble to a developer (negative photoresist causes exposed portions to be etched and covered portions to remain See Fig, 4G); and applying the developer to the semiconductor structure to dissolve the negative photoresist coating in the plurality of pillar recesses that are not exposed (as can be seen in Fig. 4G, neg would be removed in non-exposed regions). Claim 17, Kim discloses (Figs. 4A-4K) the method of claim 1, wherein the stack of layers (stack) include (Fig. 4k) a deck of alternating conduction layers (13 gets replaced by 19 in Fig. 4K, gate electrode, Para [0064]) and oxide layers (12, dielectric layer may be oxide, Para [0029]), wherein the conductive layers are used for memory cells (19 are gate electrodes for memory cell region, Para [0065]). Claim 18, Kim discloses (Figs. 4A-4K) the method of claim 1, wherein the negative photoresist coating comprises a negative photoresist (11UM may have neg which is a negative photoresist, Para [0056]). Claim 19, Kim discloses (Figs. 4A-4K) the method of claim 1, wherein the semiconductor structure is a three- dimensional (3D) memory structure (11 is the substrate in which a 3D memory device may be formed, Para [0003]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2013/0137266) as applied to claim 1 above, and further in view of Shin (US 2019/0027490). Claim 20, Chen discloses the method of claim 1. Chen does not explicitly disclose further comprising selectively locating dummy pillar regions at weak points. However, Shin discloses (Fig. 12) forming dummy pillars DCH2 to support vulnerable narrow connection portions such as GC (Para [0071]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to selectively locate the dummy pillars 304a/304b in weak points of the device 300 as dummy pillars support narrow structures and prevent them from collapsing (Shin, Para [0071]). Allowable Subject Matter Claims 2-6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the 112 rejection above and in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Regarding Claim 2 (from which claims 3-6 depend), after applying the developer and dissolving the negative photoresist coating in the plurality of pillar recesses to become operative pillars, using an etchant to punch through the bottom caps in those plurality of pillar recesses. Regarding Claim 16, wherein the stack of layers include a source material that is partially punched through for operative pillars. Claims 12-15 would be allowed if rewritten to overcome the 112 rejections above. The following is a statement of reasons for the indication of allowable subject matter: The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Regarding Claim 12 (from which claims 13-15 depend), performing an etch operation to punch through at least a portion of the bottom caps in the plurality of pillar recesses for the operative pillars… Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.G.R/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

May 12, 2023
Application Filed
Sep 25, 2023
Response after Non-Final Action
Dec 24, 2025
Non-Final Rejection — §102, §103, §112
Mar 26, 2026
Examiner Interview Summary
Mar 26, 2026
Applicant Interview (Telephonic)
Mar 30, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
96%
With Interview (+1.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 534 resolved cases by this examiner