DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention II (claims 10-20) in the reply filed on September 29, 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10, lines: 6-7 recite the limitation “the tunnel dielectric having a cross-section profile where a first thickness for a bottom wordline layer…” it is unclear if the first thickness corresponds to the tunnel dielectric element or the bottom wordline layer element. For purposes of examination this will be interpreted as “the tunnel dielectric having a cross-section profile where a first thickness of the tunnel dielectric for a bottom wordline layer…”
Claim 16, lines: 8-9 recite the limitation “a dielectric, formed over sidewalls of the memory holes, the dielectric having a cross- section profile having a first thickness for a bottom wordline layer…” it is unclear if the first thickness corresponds to the dielectric element or the bottom wordline layer element. For purposes of examination this will be interpreted as ““a dielectric, formed over sidewalls of the memory holes, the dielectric having a cross- section profile having a first thickness of the dielectric for a bottom wordline layer…” Claim 20, lines: 2-3 recite the limitation “wherein the dielectric comprises a blocking dielectric and/or a tunnel dielectric.” It is unclear if the dielectric of claim 20 is meant to be a single element or multiple elements. For purposes of examination this will be interpreted as “wherein the dielectric comprises a blocking dielectric and a tunnel dielectric.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-13, 15-16, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shim (US 2010/0213527). Claim 10, Shim discloses (Figs. 1A-1B) a three-dimensional (3D) memory device comprising: a plurality of memory tiers (LSG/CG/USG/115a, gates/inter-gate dielectric pattern, Para [0026], hereinafter “tiers”) comprising wordline layers (155, gate stack, Para [0027]) interposed between (155 are interposed with 115a) isolation layers (115a), a memory tier (CG, cell gates, Para [0027]) comprising a two-dimensional (2D) array of memory cells (as can be seen in Fig. 1A, 155 extends in two dimensions (x-y) and CG which is part of 155 would also extend in two dimensions), a plurality of vertical structures (125a, active patterns, Para [0029]) passing through memory cells in the wordline layers (125a passes through CGs) and passing through the isolation layers (125a passes through 115a), a tunnel dielectric (145d, data storage layer includes tunnel dielectric, Para [0032], hereinafter “tunnel”), formed over sidewalls of the vertical structures (tunnel is formed over sidewalls of 125a), the tunnel dielectric having a cross-section profile where a first thickness (vertical thickness of 145d at the level of LSG, hereinafter “t1”) of the tunnel dielectric for a bottom wordline layer (LSG) that is thicker than a second thickness (vertical thickness of 145d at a level of CG which is above LSG, hereinafter “t2”) of the tunnel dielectric for at least a portion of the wordline layers (155) above the bottom wordline layer (since LSG is thicker than CG, t1 would be thicker than t2, Para [0033]). Claim 11, Shim discloses (Figs. 1A-1B) the 3D memory device of claim 10, wherein a quality of the tunnel dielectric (tunnel) at the bottom wordline layers (LSG) matches a quality of the tunnel dielectric for at least one or more of a middle wordline layer (CG) and a top wordline (USG) layer (tunnel of 145d may be an oxide which is consistent throughout the layer, Para [0032]). Claim 12, Shim discloses (Figs. 1A-1B) the 3D memory device of claim 10, wherein the vertical structures (125a) comprise memory holes (125a are formed in memory holes shown in the method of Fig. 2B with hole 120). Claim 13, Shim discloses (Figs. 1A-1B) the 3D memory device of claim 10, wherein the vertical structures (125a) comprise trenches (125a are formed in trenches shown in the method of Fig. 2B with trench 120). Claim 15, Shim discloses (Figs. 1A-1B) the 3D memory device of claim 10, wherein the plurality of memory cells (CG) comprises floating gate memory cells or Charge-Trap Flash (CTF) memory cells (the memory device is NAND which is a charge trap flash memory where charge trapping layer is in 145d, Para [0007], [0032]). Claim 16, Shim discloses (Figs. 1A-1B, 2A-2G, 10) a system (Fig. 10, 1200, memory card, Para [0129) comprising: a host (Fig. 10, Host, Para [0130]), including a processor (1223, host interface for processing between 1200 and Host, Para [0130]); a three-dimensional (3D) NAND memory device (1210, memory device, which may include VNAND, Para [0007], [0130]), coupled to the host (1210 is coupled to Host as shown in Fig. 10), having, a plurality of memory tiers (Fig. 1B, LSG/CG/USG/115a, gates/inter-gate dielectric pattern, Para [0026], hereinafter “tiers”) comprising wordline layers (Fig. 1B, 155, gate stack, Para [0027]) interposed between (155 are interposed with 115a) isolation layers (115a), a memory tier (CG, cell gates, Para [0027]) comprising a two-dimensional (2D) array of memory cells (as can be seen in Fig. 1A, 155 extends in two dimensions (x-y) and CG which is part of 155 would also extend in two dimensions); a plurality of memory holes (opening where 145d is formed, hereinafter “holes”) passing through memory cells (holes pass through CG) in the wordline layers (155) and passing through the isolation layers (holes pass through 115a); a dielectric (145d, data storage layer includes dielectric, Para [0032]), formed over sidewalls of the memory holes (145d would be formed over sidewalls of holes), the dielectric having a cross- section profile having a first thickness (vertical thickness of 145d at the level of LSG, hereinafter “t1”) of the dielectric for a bottom wordline layer (LSG) that is thicker than a second thickness (vertical thickness of 145d at a level of CG which is above LSG, hereinafter “t2”) of the dielectric for at least a portion of the wordline layers above the bottom wordline layer (since LSG is thicker than CG, t1 would be thicker than t2, Para [0033]). Claim 19, Shim discloses (Figs. 1A-1B, 2A-2G, 10) the system of claim 16, wherein the plurality of memory cells (CG) comprises floating gate memory cells or Charge-Trap Flash (CTF) memory cells (the memory device is NAND which is a charge trap flash memory where charge trapping layer is in 145d, Para [0007], [0032]). Claim 20, Shim discloses (Figs. 1A-1B, 2A-2G, 10) the system of claim 16, wherein the plurality of memory cells comprises Charge-Trap Flash (CTF) memory cells (the memory device is NAND which is a charge trap flash memory where charge trapping layer is in 145d, Para [0007], [0032]), and wherein the dielectric (145d) comprises a blocking dielectric and a tunnel dielectric (145d comprises both a tunnel dielectric layer and blocking dielectric layer, Para [0032]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 2010/0213527) as applied to claims 10 and 16 above, and further in view of Ahn (US 2011/0024818). Claim 14, Shim discloses (Figs. 1A-1B) the 3D memory device of claim 10, wherein the tunnel oxide (tunnel) cross-section profile has a third thickness (vertical thickness of 145d at the level of USG, hereinafter “t3”) for a wordline proximate to a top of the vertical structures (USG is proximate to top of 125a). Shim does not explicitly disclose that third thickness substantially matches the first thickness. However, Ahn discloses (Fig. 2A) a memory device a lower selection transistor LST and upper selection transistor UST having thicknesses ranging from 10 to 1000 angstrom (Para [0032]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable of selection gate thickness (result effective at least insofar as the thickness affects the channel length of each memory cell) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). As a result, LSG and USG can be chosen to have the same thickness resulting in t3 having the same thickness as t1. Claim 18, Shim discloses (Figs. 1A-1B, 2A-2G, 10) the system of claim 16, wherein the dielectric (145d) cross-section profile has a third thickness (vertical thickness of 145d at the level of USG, hereinafter “t3”) for a wordline proximate to a top of the vertical structures (USG is proximate to top of 125a). Shim does not explicitly disclose that third thickness substantially matches the first thickness. However, Ahn discloses (Fig. 2A) a memory device a lower selection transistor LST and upper selection transistor UST having thicknesses ranging from 10 to 1000 angstrom (Para [0032]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable of selection gate thickness (result effective at least insofar as the thickness affects the channel length of each memory cell) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). As a result, LSG and USG can be chosen to have the same thickness resulting in t3 having the same thickness as t1.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shim (US 2010/0213527) as applied to claim 16 above, and further in view of Taniguchi (US 2014/0084364). Claim 17, Shim discloses (Figs. 1A-1B, 2A-2G, 10) the system of claim 16. Shim does not explicitly disclose wherein the memory holes have a depth to diameter aspect ratio of at least 25:1. However, Taniguchi discloses (Fig. 10) where memory holes 21 have an aspect ration of 20 to 40 (Para [0074]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine experimentation, “the result effective variable of hole aspect ratio (result effective at least insofar as the aspect ratio affects the etch rate when forming the memory structure) in order to optimize the functionality of the device (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), see MPEP §2144.05). Further, the specification contains no disclosure of either the critical nature of the claimed aspect ratio or any unexpected results arising therefrom and it has been held that where patentability is said to be based upon a particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension is critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). As a result, holes can be chosen to have an aspect ratio of 25 or greater.
Conclusion
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/G.G.R/Examiner, Art Unit 2812