DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on how any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 18, 21 – 23, 25 – 28 and 31 – 34 are allowed.
The following is an examiner’s statement of reasons for allowance: the prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the independent claims 18 and 25 in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper.
The prior art fails to teach a combination of all the claimed features as presented in independent claim 18 with the allowable feature being: a device comprising: a first exterior section of a printed circuit board (PCB), the first exterior section of the PCB comprising at least three conductive layers including a first outermost conductive layer of the PCB; a second exterior section of the PCB comprising at least three conductive layers; a fifth interior conductive layer disposed between the first interior conductive layer and the third interior conductive layer, and a sixth interior conductive layer disposed between the second interior conductive layer and the fourth interior conductive layer; wherein the first exterior section of the PCB further comprises a first set of vias comprising at least three vertically arranged vias; wherein the second exterior section of the PCB further comprises a second set of vias comprising at least three vertically arranged vias, wherein the interior section of the PCB further comprises: buried skip vias each corresponding to a via having ends connected to respective interior conductive layers of the interior section of the PCB that are separated by at least one layer of the interior section of the PCB, wherein the buried skip vias comprise a first buried skip via extending from the first interior conductive layer to the third interior conductive layer and bypassing the fifth interior conductive layer, and a second buried skip via extending from the second interior conductive layer to the fourth interior conductive layer and bypassing the sixth interior conductive layer; a first additional via directly underneath the first set of vias and having an end connected to the fifth interior conductive layer; and a second additional via directly underneath the second set of vias and having an end connected to the sixth interior conductive layer.
The prior art fails to teach a combination of all the claimed features as presented in independent claim 25 with the allowable feature being: a device comprising: a first exterior section of a printed circuit board (PCB), the first exterior section of the PCB comprising at least five conductive layers including a first outermost conductive layer of the PCB; a second exterior section of the PCB, the second exterior section of the PCB comprising at least five conductive layers; a fifth interior conductive layer disposed between the first interior conductive layer and the third interior conductive layer, and a sixth interior conductive layer disposed between the second interior conductive layer and the fourth interior conductive layer; the first set of vias and the second set of vias each comprising at least five vertically arranged vias; wherein the second exterior section of the PCB further comprises a third set of vias comprising at least five vertically arranged vias, the buried skip via extending from the first interior conductive layer to the third interior conductive layer and bypassing the fifth interior conductive layer, wherein the buried skip via is directly underneath the first set of vias; a first additional via directly underneath the second set of vias and having an end connected to the fifth interior conductive layer; and a second additional via directly underneath the second set of vias and having an end connected to the sixth interior conductive layer.
One close prior art Nakamura (US 2009/0236143 A1) teaches of a device comprising: a first exterior section of a printed circuit board (PCB) including a first outermost conductive layer of the PCB; a second exterior section of the PCB including a second outermost conductive layer of the PCB; and an interior section of the PCB, disposed between the first exterior section of the PCB and the second exterior section of the PCB, comprising a first interior conductive layer corresponding to a first end of the interior section, a second interior conductive layer corresponding to a second end of the interior section opposite the first end, a third interior conductive layer disposed between the first interior conductive layer and the second interior conductive layer, a fourth interior conductive layer disposed between the first interior conductive layer and the second interior conductive layer, the first set of vias extending from the first outermost conductive layer to the first interior conductive layer; the second set of vias extending from the second outermost conductive layer to the second interior conductive layer; and wherein the interior section of the PCB further comprises: buried skip vias each corresponding to a via having ends connected to respective interior conductive layers of the interior section of the PCB that are separated by at least one layer of the interior section of the PCB; an additional buried via that spans the interior section by extending from the first interior conductive layer to the second interior conductive layer; however Nakamura does not teach the first exterior section of the PCB comprising at least three conductive layers including a first outermost conductive layer of the PCB; a second exterior section of the PCB, the second exterior section of the PCB comprising at least three conductive layers including a second outermost conductive layer of the PCB; a fifth interior conductive layer disposed between the first interior conductive layer and the third interior conductive layer, and a sixth interior conductive layer disposed between the second interior conductive layer and the fourth interior conductive layer; wherein the first exterior section of the PCB further comprises a first set of vias comprising at least three vertically arranged vias, wherein the second exterior section of the PCB further comprises a second set of vias comprising at least three vertically arranged vias, wherein the buried skip vias comprise a first buried skip via extending from the first interior conductive layer to the third interior conductive layer and bypassing the fifth interior conductive layer, and a second buried skip via extending from the second interior conductive layer to the fourth interior conductive layer and bypassing the sixth interior conductive layer; a first additional via directly underneath the first set of vias and having an end connected to the fifth interior conductive layer; and a second additional via directly underneath the second set of vias and having an end connected to the sixth interior conductive layer.
Therefore claims 18, 21 – 23, 25 – 28 and 31 – 34 are allowed.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1).
Regarding Claim 1, Nakamura (US 2009/0236143 A1) discloses a device (Fig 16) comprising: an exterior section (section or region or portion of 600 including layers above the upper 622 callout; note that the claim has not structurally or physically claimed the periphery or limits of this claimed section) of a printed circuit board (PCB), the exterior section (section or region or portion of 600 including layers above the upper 622 callout) of the PCB comprising an outermost conductive layer (layer about 622a) of the PCB; and an interior section (section or region or portion of 600 including layers between the upper 622 callout and lower 622 callout; note that the claim has not structurally or physically claimed the periphery or limits of this claimed section) of the PCB, adjacent to the exterior section of the PCB, comprising a first interior conductive layer (layer of 622 at the upper 622 callout) corresponding to a first end (upper end) of the interior section (section or region or portion of 600 including layers between the upper 622 callout and lower 622 callout), a second interior conductive layer (layer of 622 at the lower 622 callout) corresponding to a second end (lower end of the section between upper 622 and lower 622) of the interior section opposite the first end, a third interior conductive layer (612 at a lower end of 610) disposed between the first interior conductive layer (layer of 622 at the upper 622 callout) and the second interior conductive layer (layer of 622 at the lower 622 callout), and a fourth interior conductive layer (upper layer at callout 612a,612) disposed between the first interior conductive layer (layer of 622 at the upper 622 callout) and the second interior conductive layer (layer of 622 at the lower 622 callout); wherein the exterior section of the PCB further comprises a set of vias (630,630 at uppermost part of 600) extending from the outermost conductive layer (at 622a) of the PCB to the first interior conductive layer (layer at upper 622 callout); and wherein the interior section of the PCB further comprises one or more buried skip vias (640 is a via shown buried within 600) each corresponding to a via having ends connected to respective interior conductive layers (layer at upper 622 callout and layer at lower 612a callout) of the interior section of the PCB that are separated by at least one layer (layer at upper 612a callout) of the interior section of the PCB, wherein the one or more buried skip vias (640) comprise a first buried skip via (640) extending from the first interior conductive layer (layer of 622 at the upper 622 callout) to the third interior conductive layer (612 at a lower end of 610); and an additional buried via (left side 650 skips other conductive layers and spans from upper 622 layer to lower 622 layer) that spans the interior section of the PCB by extending from the first interior conductive layer (layer of 622 at the upper 622 callout) to the second interior conductive layer (layer of 622 at the lower 622 callout).
Nakamura does not explicitly disclose the PCB comprising at least three conductive layers including an outermost conductive layer and comprising at least three vertically arranged vias, the set of vias extending from the outermost conductive layer.
Takeuchi (US 2006/0289202 A1) teaches of a device (Fig 4,1) comprising: an exterior section (section or portion of 100 about 110-140; [0014,0033]) of a printed circuit board (PCB) (100), the exterior section of the PCB comprising at least three conductive layers (205 at 130,120,110,105; [0014,0033]) including an outermost conductive layer (105; 205 at 110) of the PCB; and an interior section (section of portion about 140,150,145) of the PCB, adjacent to the exterior section of the PCB, comprising a first interior conductive layer (210,205 at 140,135) corresponding to a first end of the interior section; wherein the exterior section of the PCB further comprises a set of vias (200,305; [0014,0033]) comprising at least three vertically arranged vias (200,305), the set of vias (200,305) extending from the outermost conductive layer (105,205 at 110) of the PCB to a first interior conductive layer (205 at 140,135; 210).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as disclosed by Nakamura, comprising at least three conductive layers including an outermost conductive layer and comprising at least three vertically arranged vias, the set of vias extending from the outermost conductive layer of the PCB to the first interior conductive layer as taught by Takeuchi, in order to provide very dense surface mount assemblies, high density packages, provide higher density circuits, high packing density, improve routing density, prevent wasting of PCB space, connect layers of a multi-layered PCB, improve electrical and mechanical characteristics, provide the capability of routing or escaping standard and fine pitch devices and provide reliability (Takeuchi, [0001-0005,0015-0018,0045]. An increase in the number of conductive layers also would allow increases in electrical connections to components mounted on and within a board, thus potentially allowing for more functional uses for the board. The combination would also potentially provide a higher density wiring board, provide space saving, provide a larger number of layers, provide more advanced features, allow for additional ground layers, allow for additional signal layers, meet the demands of increasing handling of information on systems for mounting components, and allow for a denser arrangement. Please note that in the instant application, page 4 [0014], page 5, [0017], page 9 [0027], page 12 [0036], page 20 [0061] – page 23 [0072], Applicant has not disclosed any criticality for the claimed limitations.
Regarding Claim 4, Nakamura further discloses the device (Fig 16) of claim 1, wherein the set of vias (630,630 at uppermost part of 600) comprises a set of stacked vias (see Fig 16).
Regarding Claim 8, Nakamura further discloses the device (Fig 16) of claim 1, further comprising a second exterior section (section or portion below lower 622 callout) of the PCB adjacent to the interior section of the PCB, wherein the second exterior section of the PCB comprises: a second outermost conductive layer (lowermost 622a) of the PCB; and a second set of vias (630) formed from the second outermost conductive layer to the second conductive layer (layer at lower 622 callout).
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1) as applied to claim 1 above and further in view of Smith (US 2023/0319978 A1) and Ikeda (US 2007/0271783 A1).
Regarding Claim 2, Nakamura in view of Takeuchi teaches the limitations of the preceding claim.
Nakamura does not disclose the device of claim 1, wherein the interior section of the PCB further comprises: an additional via directly underneath the set of vias and having an end connected to a fifth interior conductive layer of the interior section of the PCB, wherein the fifth interior conductive layer is disposed between the first interior conductive layer and the third interior conductive layer.
Smith (US 2023/0319978 A1) teaches of a device (Fig 3) comprising a fifth interior conductive layer (312) disposed between a first interior conductive layer (332) and a third interior conductive layer (314), and a sixth interior conductive layer (316) disposed between a second interior conductive layer (336) and a fourth interior conductive layer (334).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, wherein the fifth interior conductive layer is disposed between the first interior conductive layer and the third interior conductive layer as taught by Smith, in order to allow for additional ground layers, provide additional signal layers, improve utilization of skip vias, improve utilization of microvias, and meet the demands of increasing handling of information and systems for mounting components (Smith, [0002-0003,0017-0035]).
Ikeda teaches of a device (Fig 1) wherein a first exterior section (section or portion with 70) of a PCB comprising at least conductive layers (wirings at surfaces of 70 near 70a,70b); a second exterior section (section or portion about 90) of the PCB, the second exterior section (90) of the PCB comprising at least conductive layers (wirings at surfaces of 90 near 90a,90b); wherein the first exterior section of the PCB further comprises a first set of vias (70a) and a second set of vias (vias at 70,70 without callout on left side of Fig 1) extending from a first outermost conductive layer (uppermost wiring atop 70) to a first interior conductive layer (30), the second set of vias (vias at 70,70 without callout on left side of Fig 1); wherein the second exterior section of the PCB further comprises a third set of vias (90b) extending from the second outermost conductive layer (layer at lowermost 90b) to the second interior conductive layer (32), a buried skip via (51,53) bypassing the interior conductive layer (40,42), wherein the buried skip via (51) is directly underneath the first set of vias (70a,70a); a first additional via (54) directly underneath the second set of vias (70b,70b) and having an end connected to the interior conductive layer; and a second additional via (54 in 24 at furthest left of Fig 1 without callout) directly underneath the second set of vias (vias at 70,70 without callout on left side of Fig 1) and having an end connected to the interior conductive layer.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi and Smith, wherein the interior section of the PCB further comprises: an additional via directly underneath the set of vias and having an end connected to an interior conductive layer of the interior section of the PCB as taught by Ikeda, in order to allow for a more dense arrangement, reduce pitch, reduce loop inductance, reduce or suppress delays to power or ground or signals (Ikeda, [0007-0016,0055,0056]). The combination of Nakamura in view of Smith and Ikeda would teach wherein the interior section of the PCB further comprises: an additional via directly underneath the set of vias and having an end connected to a fifth interior conductive layer of the interior section of the PCB, since it has been held that rearranging parts of an invention involves only routine skill in the art (In re Japikse, 86 USPQ 70) and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8) in order to allow for additional ground layers, provide additional signal layers, improve utilization of skip vias, improve utilization of microvias, meet the demands of increasing handling of information on systems for mounting components, in order to allow for a more dense arrangement, reduce pitch, reduce loop inductance, reduce or suppress delays to power or ground or signals. Please note that in the instant application, page 4 [0014], page 5, [0017], page 9 [0027], page 12 [0036], Applicant has not disclosed any criticality for the claimed limitations.
Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1) as applied to claim 1 above and further in view of Leitgeb (US 2019/0378801 A1).
Regarding Claim 3, Nakamura further discloses the device (Fig 16) of claim 1, wherein each via (630,630 at uppermost part of 600) of the set of vias is a via ([0008] with a minute size). Note that the claim language has not structurally defined “microvia”.
Nakamura does not explicitly disclose wherein each via of the set of vias is a microvia having a depth-to-diameter aspect ratio of less than or equal to about 1:1.
Takeuchi teaches of device (Fig 1,3) wherein each via (200,305) of a set of vias is a microvia ([0017-0049]).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, wherein each via of the set of vias is a microvia as taught by Takeuchi, in order to reduce layer count, improve mechanical and electrical characteristics, provide access to multiple layers, provide capability of routing or escaping standards (Takeuchi, [0017-0049]).
Leitgeb teaches ([0034]) a microvia having a depth-to-diameter aspect ratio of less than or equal to about 1:1.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, comprising a microvia having a depth-to-diameter aspect ratio of less than or equal to about 1:1 as taught by Leitgeb, in order to meet IPC standards and accommodate high density (Leitgeb, [0034]).
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1) as applied to claim 1 above and further in view of Saiki (US 2008/0083560 A1).
Regarding Claim 5, Nakamura in view of Takeuchi teaches the limitations of the preceding claim.
Nakamura does not disclose the device of claim 1, wherein the set of vias comprises a set of staggered vias.
Saiki teaches of a device (Fig 5) wherein a set of vias (5; [0069]) comprises a set of staggered vias (5i,5).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, wherein the set of vias comprises a set of staggered vias as taught by Saiki, in order to disperse stress and reduce occurrence of cracks (Saiki, Abstract, [0004,0005,0037,0039,0042,0053,0061,0066,0069]).
Claim(s) 7 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1) as applied to claim 1 above and further in view of Ikeda (US 2007/0271783 A1).
Regarding Claim 7, Nakamura in view of Takeuchi teaches the limitations of the preceding claim.
Nakamura does not disclose the device of claim 1, wherein the one or more buried skip vias further comprise an additional a second buried skip via extending from the second interior conductive layer to the fourth interior conductive layer.
Ikeda (US 2007/0271783 A1) teaches of a device (Fig 1) comprising: an exterior section (section or portion with 70) of a printed circuit board (PCB), the exterior section comprising an outermost conductive layer (upper layer with pads connecting 70b to 60b; [0047,0071]) of the PCB; and an interior section (section or portion with 30,24,40,22,42,26,32) of the PCB, adjacent to the exterior section (70), comprising a first interior conductive layer (30) corresponding to a first end (upper end) of the interior section, a second interior conductive layer (32) corresponding to a second end (lower end) of the interior section opposite the first end, a third interior conductive layer (42) disposed between the first interior conductive layer (30) and the second interior conductive layer (32), and a fourth interior conductive layer (40) disposed between the first interior conductive layer (30) and the second interior conductive layer (32); wherein the exterior section (70) further comprises a set of vias (70a,70b) extending from the outermost conductive layer (upper layer with pads connecting 70b to 60b) of the PCB to the first interior conductive layer (30); and wherein the interior section further comprises buried skip vias (51,53 shown to be buried within the interior section and skipping layers 40 and 42 respectively) each corresponding to a via (51,53) having ends connected to respective interior conductive layers (30,32) of the interior section that are separated by at least one layer (22) of the interior section, and wherein the buried skip vias (51,53) comprise a first buried skip via (51) extending from the first interior conductive layer (30) to the third interior conductive layer (42), wherein the one or more buried skip vias (51,53) further comprise an additional a second buried skip via (53) extending from the second interior conductive layer (32) to the fourth interior conductive layer (40).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, wherein the set of vias comprises a set of staggered vias wherein the one or more buried skip vias further comprise an additional a second buried skip via extending from the second interior conductive layer to the fourth interior conductive layer as taught by Ikeda, in order to allow for a more dense arrangement, reduce pitch, reduce loop inductance, reduce or suppress delays to power or ground or signals, (Ikeda, [0007-0016,0055,0056]).
Claim(s) 30 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura (US 2009/0236143 A1) in view of Takeuchi (US 2006/0289202 A1) as applied to claim 1 above and further in view of Frosch (US 2012/0103664 A1).
Regarding Claim 30, Nakamura in view of Takeuchi teaches the limitations of the preceding claim.
Nakamura does not explicitly disclose the device of claim 1, wherein the interior section comprises at least 10 conductive layers.
Frosch (US 2012/0103664 A1) teaches of a device (Fig 2) comprising a plurality of conductive layers (12,13).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the device as taught by Nakamura in view of Takeuchi, wherein the interior section comprises at least 10 conductive layers, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art, in order to increase conductive material content in a circuit board which would provide some at least partial protection from fire, smoke and flame (Frosch, [0002-0009]). St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. An increase in the number of conductive layers also would allow increases in electrical connections to components mounted on and within a board, thus potentially allowing for more functional uses for the board. The combination would also potentially provide a higher density wiring board, provide space saving, provide a larger number of layers, provide more advanced features, allow for additional ground layers, allow for additional signal layers, meet the demands of increasing handling of information on systems for mounting components, and allow for a denser arrangement. Please note that in the instant application, page 4 [0014], page 5, [0017], page 9 [0027], page 12 [0036], page 20 [0061] – page 23 [0072], Applicant has not disclosed any criticality for the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSHN K VARGHESE whose telephone number is (571)270-7975. The examiner can normally be reached M-Th: 900 am-300 pm.
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/ROSHN K VARGHESE/Primary Examiner, Art Unit 2896