DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Integrated Circuit Device with PN Junction”
Appropriate correction is required.
Claim Objections
6. Claim 21 is objected to because of the following informalities:
Claim 21, ln 10 recites “second supporting a base contact” which should recite “second trench supporting a base contact.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claim 21-22 and 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the limitation "the second substrate region” in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination on the merits, “the second substrate region” will be interpreted as “a second substrate region” in accordance with the applicant’s disclosure.
The dependent claims necessarily inherit the indefiniteness of the claims on which
they depend.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1-14 and 16-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Brown, Adam R. (Pub No. US 20010041407 A1) (hereinafter, Brown).
Brown, Fig 7: Manufacturing stage of trench-gate MOSFET device
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Re Claim 1, Brown teaches a method of manufacturing a PN junction, comprising the following successive steps:
forming at least one trench (First/second trench; 20/40; Fig 7; ¶[0039]) in a semiconductor substrate (N-type first layer/body region; 14/15; Fig 7; ¶[0044]) of a first conductivity type (N-type; ¶[0044]); and
filling said at least one trench with a semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) of a second conductivity type (P-type; ¶[0041]), different from the first conductivity type.
Re Claim 2, Brown teaches the method according to claim 1, wherein at least two trenches (Two trenches; 40; Fig 7; ¶[0039]) are formed in said substrate (N-type first layer/body region; 14/15; Fig 7; ¶[0044]).
Re Claim 3, Brown teaches the method according to claim 1, wherein forming at least one trench (First/second trench; 20/40; Fig 7; ¶[0039]) comprises:
forming a layer (Etchant mask; 52; Fig 7; ¶[0055]) made of silicon nitride (Silicon nitride; ¶[0055]);
patterning (Removing part of etchant mask 52; ¶[0055]) the layer of silicon nitride to include an opening (Windows; 52A; Fig 7; ¶[0055]) defining a hard mask (Per ¶[0055]) etchant mask 52 defines a hard mask); and
etching the at least one trench through said opening.
Re Claim 4, Brown teaches the method according to claim 3, wherein the layer (Etchant mask; 52; Fig 7; ¶[0055]) made of silicon nitride (Silicon nitride; ¶[0055]) is in contact with an upper surface (Upper surface of body region 15; Fig 7) of the semiconductor substrate (N-type first layer/body region; 14/15; Fig 7; ¶[0044]).
Brown, Fig 8: Depositing semiconductor material in trench
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Re Claim 5, Brown teaches the method according to claim 1, wherein filling said at least one trench (First/second trench; 20/40; Fig 7; ¶[0039]) with a semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) comprises performing a furnace deposition (Per ¶[0048] semiconductor material 41 comprises a step of the deposition process wherein a dopant which is out-diffused with a standard furnace at 1000 degree C) of said semiconductor material.
Re Claim 6, Brown teaches the method according to claim 1, wherein filling said at least one trench (First/second trench; 20/40; Fig 7; ¶[0039]) with a semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) comprises performing an epitaxial deposition (Per ¶[0047] the material 41 may alternatively be boron doped selectively grown epitaxial (SEG) silicon) of said semiconductor material.
Brown, Fig 15: Embodiment of MOSFET device with PN Junctions
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Re Claim 7, Brown teaches the method according to claim 1, wherein the PN junction (P-n junction between semiconductor material 41, 42, drain region 14 and source electrode 23; Fig 15; ¶[0041]) forms a diode (Per ¶[0041] the said device forms an avalanche diode current path from the drain region through the localised region to the source electrode).
Re Claim 8, Brown teaches the method according to claim 1, wherein the PN junction (P-n junction includes source 13, body 15, and drain region 14 of each transistor constituting a bipolar transistor; ¶[0041]) forms part of a bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]).
Re Claim 9, Brown teaches the method according to claim 8, wherein an emitter region (Source region; 13; Fig 15; ¶[0039]) of said bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]) is formed by the PN junction (P-n junction includes source 13, body 15, and drain region 14 of each transistor constituting a bipolar transistor; ¶[0041]).
Re Claim 10, Brown teaches the method according to claim 8, wherein a collector region (Drain region; 14; Fig 15; ¶[0039]) of said bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]) is formed by the PN junction (P-n junction includes source 13, body 15, and drain region 14 of each transistor constituting a bipolar transistor; ¶[0041]).
Brown, Fig 14: MOSFET Device with Avalanche Breakdown Region
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Re Claim 11, Brown teaches an integrated circuit, comprising:
a doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15; Fig 14; ¶[0044]) of a first conductivity type (N-type; ¶[0044]);
trenches (First/second trench; 20/40; Fig 7; ¶[0039]) in the doped semiconductor substrate; and
a first region (Trench 40 on left-hand side of device comprising semiconductor material 41; Fig 8) in one trench of said trenches (Second trench; 40; Fig 7; ¶[0039]) made of a first semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) of a second conductivity type (P-type; ¶[0041]), different from the first conductivity type, wherein said first region has a uniform doping (Per ¶[0047] material 41 is in-situ doped, of which uniform doping is an inherent feature), to form a first PN junction (A first p-n junction between n-type first layer 14 and p-type semiconductor material 41; Fig 7).
Re Claim 12, Brown teaches the integrated circuit according to claim 11, further comprising a second region (Trench 40 on right-hand side of device comprising semiconductor material 41; Fig 8) in another trench of said trenches (First/second trench; 20/40; Fig 7; ¶[0039]) made of a second semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) of the second conductivity type (P-type; ¶[0041]), different from the first conductivity type, wherein said second region has a uniform doping (Per ¶[0047] material 41 is in-situ doped, of which uniform doping is an inherent feature).
Re Claim 13, Brown teaches the integrated circuit according to claim 12, wherein said doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15/64; Fig 14; ¶[0044]) comprises at least one doped portion (Avalanche breakdown region; 64; Fig 14; ¶[0065]) of the first conductivity type (N-type; ¶[0044]) having a higher doping level (Higher doping concentration; ¶[0065]) than the other doped substrate portions (N-type first layer; 14; Fig 7; ¶[0044]) of the first conductivity type, said portion surrounding (Avalanche breakdown region 64 surrounds entire base of trench 40; Fig 14) said first region (Trench 40 on left-hand side of device comprising semiconductor material 41; Fig 8), and
wherein said portion surrounds an assembly (Avalanche breakdown region 64 surrounds both left and right-hand side trenches 40; Fig 14) of said first and second regions (Trench 40 on right-hand side of device comprising semiconductor material 41; Fig 8).
Re Claim 14, Brown teaches the integrated circuit according to claim 12, wherein the first (Trench 40 on left-hand side of device comprising semiconductor material 41; Fig 8) and second regions (Trench 40 on right-hand side of device comprising semiconductor material 41; Fig 8) form the first PN junction (A first p-n junction between n-type first layer 14 and p-type semiconductor material 41 on left side; Fig 7) and a second PN junction (A second p-n junction between n-type first layer 14 and p-type semiconductor material 41 on right side; Fig 7) for a bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]).
Re Claim 16, Brown teaches the integrated circuit according to claim 12, further comprising at least one trench (Trenches; 20; Fig 14; ¶[0039]) in the doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15; Fig 14; ¶[0044]) surrounding first (Trench 40 on left-hand side of device comprising semiconductor material 41; Fig 8) and second regions (Trench 40 on right-hand side of device comprising semiconductor material 41; Fig 8).
Re Claim 17, Brown teaches the integrated circuit according to claim 11, wherein said doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15; Fig 14; ¶[0044]) comprises at least one doped portion (Avalanche breakdown region; 64; Fig 14; ¶[0065]) of the first conductivity type (N-type; ¶[0044]) having a higher doping level (Higher doping concentration; ¶[0065]) than the other doped substrate portions (N-type first layer; 14; Fig 7; ¶[0044]) of the first conductivity type, said portion surrounding (Avalanche breakdown region 64 surrounds entire base of trench 40; Fig 14) said first region (Trench 40 on left-hand side of device comprising semiconductor material 41; Fig 8).
Re Claim 18, Brown teaches an integrated circuit, comprising:
a doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15/64; Fig 14; ¶[0044]) of a first conductivity type (N-type; ¶[0044]);
wherein said doped semiconductor substrate includes a first substrate region (Avalanche breakdown region; 64; Fig 14; ¶[0065]) and a second substrate region (N-type first layer; 14; Fig 7; ¶[0044]), said first substrate region having a higher doping level (Higher doping concentration; ¶[0065]) than the second substrate region;
a plurality of trenches (First/second trenches; 20/40; Fig 7; ¶[0039]) extending into the second substrate region of the doped semiconductor substrate;
a first semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) of a second conductivity type (P-type; ¶[0041]) filling said plurality of trenches to form a PN junction (P-n junction between semiconductor material 41, 42, drain region 14 and source electrode 23; ¶[0041]) for a diode (Per ¶[0041] the said device forms an avalanche diode current path from the drain region through the localised region to the source electrode); and
pad material (Conductive gate and/or mask; 21/53; Figs 14/10; ¶[0068]) covering an upper surface (21 covers portions of upper surfaces of 14 and 15; Fig 14) of the first and second substrate regions of the doped semiconductor substrate.
Re Claim 19, Brown teaches the integrated circuit of claim 18, wherein said pad material (Conductive gate and/or mask; 21/53; Figs 14/10; ¶[0068]) comprises polysilicon (Polycrystalline silicon; ¶[0068]).
Re Claim 20, Brown teaches the integrated circuit of claim 18, wherein said pad material (Conductive gate and/or mask; 21/53; Figs 14/10; ¶[0068]) comprises silicon oxide (Silicon dioxide; ¶[0061]).
Re Claim 21, Brown teaches an integrated circuit, comprising:
a doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15/64; Fig 14; ¶[0044]) of a first conductivity type (N-type; ¶[0044]);
a plurality of first trenches (Second trenches; 40; Fig 7; ¶[0039]) extending into a second substrate region (N-type first layer; 14; Fig 7; ¶[0044]) of the doped semiconductor substrate;
a first semiconductor material (Semiconductor material; 41; Fig 8; ¶[0041]) of a second conductivity type (P-type; ¶[0041]) filling said plurality of trenches to form two PN junctions (P-type material 41 forms PN junctions with N-type material 14; Fig 8; ¶[0058]) for an emitter (Source region; 13; Fig 15; ¶[0039]) and a collector (Drain region; 14; Fig 15; ¶[0039]) of a bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]) having the doped semiconductor substrate forming a base (Body region; 15; Fig 14; ¶[0041]) of the bipolar transistor;
a second trench (First trench in middle between trenches 40; 20; Fig 14; ¶[0039]) extending into the second substrate region of the doped semiconductor substrate to surround the bipolar transistor;
a region (Region of drain region 14 below 21; Fig 15) of the doped semiconductor substrate beyond the second trench supporting a base contact (Gate material; 21; fig 15; ¶[0045]) for the bipolar transistor; and
emitter and collector contacts (Source electrode contacting each material 41; 23; Fig 15; ¶[0040]) supported by the first semiconductor material in the plurality of first trenches.
Examiner notes that the p-n junction formed by p-type material 41 and n-type material 14 do not anticipate the emitter and the collector, however, according to the claim language, "a first semiconductor material…. Filling said plurality of trenches to form two PN junctions for an emitter and a collector of a bipolar transistor" the p-n junction of Brown, in its broadest reasonable interpretation, are formed for an emitter and a collector of a bipolar transistor, wherein the bipolar transistor of Fig 14 of Brown comprises the vertical arrangement of the source region (13), body (15), and drain region (14).
Re Claim 22, Brown teaches the integrated circuit of claim 21, further comprising a third trench (One of the outer trenches; 20; Fig 14) extending into the second substrate region (N-type first layer; 14; Fig 7; ¶[0044]) of the doped semiconductor substrate (N-type first layer/body region/Avalanche breakdown region; 14/15/64; Fig 14; ¶[0044]) to surround both the second trench (First trench in middle between trenches 40; 20; Fig 14; ¶[0039]) and the bipolar transistor (NPN parasitic bipolar transistor; ¶[0041]), wherein said third trench is separate from said second trench (First trench in middle between trenches 40; 20; Fig 14; ¶[0039]).
Re Claim 23, Brown teaches the integrated circuit of claim 22, wherein the second (First trench in middle between trenches 40; 20; Fig 14; ¶[0039]) and third trenches (One of the outer trenches; 20; Fig 14) are shallower (Trenches 20 have less depth than trench 40; Fig 15) than the plurality of first trenches (Second trenches; 40; Fig 7; ¶[0039]).
Re Claim 24, Brown teaches the integrated circuit of claim 21, wherein the second trench (First trench in middle between trenches 40; 20; Fig 14; ¶[0039]) is shallower (Middle trench 20 has less depth than trenches 40; Fig 14) than the plurality of first trenches (Second trenches; 40; Fig 7; ¶[0039]).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Brown, Adam R. (Pub No. US 20010041407 A1) (hereinafter, Brown) as applied to claim 14 above, and further in view of Kar, Ayan et al. (Pub No. US 20220415880 A1) (hereinafter, Kar).
Kar, Fig 1I: Integrated circuit with PNP bipolar transistor
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Re Claim 15, Brown does not teach the integrated circuit according to claim 14, wherein the first region is an emitter of the transistor and the second region is a collector of the transistor.
In the same field of endeavor, Kar teaches the integrated circuit according to claim 14, wherein the first region (Left side region comprising of P-type epitaxial structures 116I; Fig 1I; ¶[0042]) is an emitter (Emitter terminal of PNP bipolar transistor; Fig 1I; ¶[0040]) of the transistor and the second region (Right side region comprising of P-type epitaxial structures 116I; Fig 1I; ¶[0042]) is a collector (Collector terminal of PNP bipolar transistor; Fig 1I; ¶[0040]) of the transistor (May be a bipolar transistor; ¶[0067]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used the first region as an emitter of the transistor and the second region as a collector of the transistor, as taught by Kar for the integrated circuit of Brown. One would have been motivated to do this with a reasonable expectation of success because the back-to-back PN junctions enable bipolar and silicon-controlled rectifier solutions, for purposes such as thermal sensing and thermal calibration. Further, the said arrangement of PNP bipolar transistor may allow for backside metal interconnects to be enabled in the integrated circuit device, as suggested by Kar (¶¶[0022, 0067]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Rana, Uzma B. et al. (Pub No. US 20220254774 A1) discloses a bipolar transistor stack within a substrate, comprising of PNP or NPN junction, in between doped semiconductor regions, connected to electrical contacts.
[2] Grivna, Gordon M. Mesa (Pub No. US 20170365678 A1) discloses an embodiment of a semiconductor device includes forming an active region that extends vertically into the semiconductor material in which the semiconductor device is formed. The active region may include a P-N junction or alternately a gate or a channel region of an MOS transistor.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817