DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 25 November 2025 have been fully considered but they are respectfully not found persuasive.
Regarding the argument relating to the rejection of claim 1, wherein Applicant submits that one of ordinary skill in the art would have no motivation to combine the disclosures of Bhadauriya (D1) and Burrows (D2) (Remarks; page 7). Examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, both the disclosures of D1 and D2 are in the field of semiconductors and/or semiconductor processing. D1 is merely silent regarding fluidly isolating the multiple precursors (D1; ¶0144) before introduction into the processing chamber. D2 teaches a clear benefit in ¶0028 of “The injection block 118 includes a plurality of fluidly isolated precursor delivery channels, which prevent premature mixing of supplied precursor gases”. Even though the primary example given throughout D2 are not the same precursors as in D1, D2 states in ¶0030 that “gallium nitride, other Group III/V materials, and other materials” are applicable.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the semiconductor processing device of D2 in the method of D1, obtaining the benefit described in ¶0028 of D2 of preventing premature mixing of precursor gases.
Regarding the argument relating to the rejection of claim 1, wherein Applicant submits that the rejection of record over D1 in view of D2 is based on impermissible hindsight (Remarks; page 7). Examiner respectfully disagrees.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Although D1 “does not provide any suggestion that premature mixing of the allegedly equivalent deposition precursors is problematic”, knowledge is gleaned from D2 that provides a clear benefit (prevent premature mixing as described in ¶0028) that is applicable to many materials (D2; ¶0030) for the deposition of precursors.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the semiconductor processing device of D2 in the method of D1, obtaining the benefit described in ¶0028 of D2 of preventing premature mixing of precursor gases.
Regarding the argument relating to the rejection of claims 12 and 18, wherein Applicant submits that one of ordinary skill in the art would have no motivation to combine the disclosures of Bhadauriya (D1) and Xue (D5) (Remarks, page 8). Examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, both the disclosures of D1 and D5 are in the field of semiconductors and/or semiconductor processing. D1 is merely silent regarding utilizing a dual channel showerhead to fluidly isolate the multiple precursors (D1; ¶0144) before introduction into the processing chamber. D5 teaches a clear benefit in ¶0026 and ¶0051 of utilizing a dual-channel showerhead to maintain and fluidly separate the precursors to prevent reaction until they are delivered into the processing region. Even though the primary example given throughout D5 are not the same precursors as in D1, D5 states in ¶0022 that the deposited layer may be a suitable semiconductor processing material deposited in a CVD chamber (as in D1; ¶0007).
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual channel showerhead configuration of D5 for the showerhead of D1 in the method of D1 in order to prevent the precursors of the method of D1 from contacting one another prematurely and reacting before reaching the substrate processing area (D5; ¶0026, ¶0051).
Regarding the argument relating to the rejection of claims 12 and 18, wherein Applicant submits that the rejection of record over D1 in view of D5 is based on impermissible hindsight (Remarks; page 8-9). Examiner respectfully disagrees.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Applicant submits that D1 “does not provide any suggestion that premature mixing of the allegedly equivalent deposition precursors is problematic” and that D5 “relates to an entirely different deposition process”. D1 and D5 are both in the field of semiconductors and/or semiconductor processing, and both are applicable to deposition processes in CVD chambers (D1 ¶0007 and D5 ¶0022), wherein D5 is also applicable to a suitable semiconductor processing material. Furthermore, knowledge is gleaned from D5 that provides a clear benefit to utilize a dual channel showerhead when using different precursors, in ¶0026 and ¶0051, to maintain and fluidly separate the precursors to prevent reaction until they are delivered into the processing region.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual channel showerhead configuration of D5 for the showerhead of D1 in the method of D1 in order to prevent the precursors of the method of D1 from contacting one another prematurely and reacting before reaching the substrate processing area (D5; ¶0026; ¶0051).
Furthermore, it is noted that the specific type of deposition and type of layer that is to be deposited are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Sonal Bhadauriya et al. (US 20250132157 A1; hereinafter D1) in view of Brian Burrows et al. (US 20200332437 A1; hereinafter D2).
Regarding Claim 1, D1 teaches a semiconductor processing method (Fig. 2) comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber (¶0006; “providing a substrate on a substrate holder in a processing chamber; exposing a top surface portion of the substrate to a metal-containing precursor (e.g., a Mo-containing precursor) and one or more optional deposition precursors”; ¶0026; “cause exposure of a top surface portion of a substrate to a Mo-containing precursor and one or more deposition precursors within the processing chamber”), wherein the deposition precursors comprise a silicon-containing precursor (¶0030; “In any embodiment herein, the one or more deposition precursors is selected from the group consisting of a carbon-containing precursor, a silicon-containing precursor, and a boron-containing precursor”; ¶0032; “the silicon-containing precursor includes a silane compound, an organosilane compound, an alkyl silane compound, an alkoxy silane compound, a silanol compound, a siloxane compound, an aminosilane compound, a cyclic azasilane compound, a halosilane compound, or an inorganic silane compound”) and a metal-containing precursor (¶0029; ¶0230), and wherein a substrate (Fig. 1; 111; ¶0139) is housed within the processing region (¶0026 quoted above);
generating plasma effluents of the deposition precursors (as described in ¶0005, ¶0013, ¶0147, ¶0161-¶0162, ¶0170, ¶0174); and
forming a layer of silicon-and-metal-containing material (Fig. 1; the Mo and Si containing layer 113; ¶0230) on the substrate (111).
D1 is silent regarding wherein the silicon-containing precursor and the metal-containing precursor are fluidly isolated prior to reaching the processing region.
However, in the same semiconductor field of endeavor, D2 teaches a semiconductor processing device (Fig. 1) with chamber capable of providing precursors to a processing area (128; ¶0027) containing a substrate (113; ¶0021) in order to deposit a layer. D2 discloses in ¶0028 “The injection block 118 includes a plurality of fluidly isolated precursor delivery channels” applicable to many materials (¶0030).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the semiconductor processing device of D2 in the method of D1, fluidly isolating the deposition precursors in order to prevent premature mixing of supplied precursor gases (as disclosed in ¶0028 of D2).
Regarding Claim 2, modified D1 teaches the semiconductor processing method of claim 1, wherein the silicon-containing precursor comprises silane (SiH4) or disilane (Si2H6) (D1; ¶0230).
Regarding Claim 3, modified D1 teaches the semiconductor processing method of claim 1, wherein the metal-containing precursor comprises one or more of tungsten, molybdenum, cobalt, tantalum, ruthenium, titanium, rhenium, hafnium, or zirconium (D1; ¶0029).
Regarding Claim 4, modified D1 teaches the semiconductor processing method of claim 1, wherein the metal-containing precursor further comprises a halogen (D1; ¶0029; “a molybdenum halide compound”).
Regarding Claim 5, modified D1 teaches the semiconductor processing method of claim 1, wherein the deposition precursors further comprise one or more of a boron-containing precursor, a carbon-containing precursor, or a nitrogen-containing precursor (D1; ¶0030; “In any embodiment herein, the one or more deposition precursors is selected from the group consisting of a carbon-containing precursor, a silicon-containing precursor, and a boron-containing precursor”).
Regarding Claim 6, modified D1 teaches the semiconductor processing method of claim 1, further comprising: cycling a flow rate of the deposition precursors, wherein a flow rate of the metal- containing precursor is greater than a flow rate of the silicon-containing precursor during a first period of time, and wherein the flow rate of the metal-containing precursor is less than a flow rate of the silicon-containing precursor during a second period of time (as described in D1 ¶0171-0172; wherein the Mo-precursor is pulsed for a first period of time, and then the silicon {deposition} precursor is pulsed for a second period of time, during the Mo-precursor pulse the flow rate is higher than the deposition precursor {that is not pulsed at the first period of time} and during the silicon {deposition} precursor pulse the flow rate is higher than the Mo-precursor {that is not pulsed at the second period of time}, and the cycles may be repeated until the desired thickness is obtained).
Regarding Claim 7, modified D1 teaches the semiconductor processing method of claim 1, wherein the layer of silicon-and-metal-containing material is characterized by a metal concentration of greater than or about 20 at.% (up to 65% Mo; D1; ¶0038).
Regarding Claim 8, modified D1 teaches the semiconductor processing method of claim 1, further comprising: pre-treating the substrate prior to forming the layer of silicon-and-metal- containing material (D1; ¶0010; “the method further includes (e.g., before said depositing): pretreating the top surface portion of the substrate. In particular embodiments, said pretreating thereby provides a pretreated surface being disposed between the substrate and the Mo-containing layer after said depositing”).
Regarding Claim 10, modified D1 teaches the semiconductor processing method of claim 8, further comprising: subsequent pre-treating the substrate (as described in D1 ¶0151, the pre-treatment can come before depositing the interfacial growth layer), forming a seed layer on the substrate (D1; ¶0009; an interfacial growth layer if formed on the substrate).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D2 and Seshadri Ganguli et al. (US 20120264291 A1; hereinafter D3).
Regarding Claim 9, modified D1 teaches the semiconductor processing method of claim 8, wherein pre-treating the substrate comprises: providing a nitrogen-containing precursor to the processing region of the semiconductor processing chamber; and contacting the substrate with the nitrogen-containing precursor (as described in D1; ¶0150 with the intent of improving adhesion).
D1 is silent regarding generating plasma effluents of the nitrogen-containing precursor; and contacting the substrate with the plasma effluents of the nitrogen- containing precursor (for the pretreatment process).
In the same field of endeavor, D3 teaches generating plasma effluents of a nitrogen-containing precursor to contact a substrate in a semiconductor processing device with the purpose of pre-treating the substrate for the following deposited layers (D3; ¶0175-¶0181).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to generate plasma effluents of the nitrogen-containing precursor (of D3) in the method of D1 in order to improve adhesion of the subsequently deposited layer (D3; ¶0175).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D2 and Eswaranand Venkatasubramanian et al. (WO 2018144198 A1; hereinafter D4).
Regarding Claim 11, modified D1 teaches the semiconductor processing method of claim 10, wherein the seed layer comprises a boron-containing material (D1; ¶0009; boron containing material).
D1 is silent about the boron containing interfacial growth layer comprising an amorphous boron-containing material.
In the same field of endeavor, D6 teaches a method of forming a hardmask film on a seed layer of amorphous boron carbide (D4; ¶0076), along with other equivalent examples of materials for seed layers (D4; ¶0047).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the amorphous boron-containing seed layer of D4 for the boron-containing interfacial growth layer of D1 in order to provide high adhesion at the interface (D4; ¶0080).
Claims 12-18 are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of Jun Xue et al. (WO 2016149541 A1; hereinafter D5).
Regarding Claim 12, D1 teaches a semiconductor processing method comprising:
providing deposition precursors to a processing region of a semiconductor processing chamber (¶0006; “providing a substrate on a substrate holder in a processing chamber; exposing a top surface portion of the substrate to a metal-containing precursor (e.g., a Mo-containing precursor) and one or more optional deposition precursors”; ¶0026; “cause exposure of a top surface portion of a substrate to a Mo-containing precursor and one or more deposition precursors within the processing chamber”), wherein the deposition precursors comprise a silicon-containing precursor (¶0030; “In any embodiment herein, the one or more deposition precursors is selected from the group consisting of a carbon-containing precursor, a silicon-containing precursor, and a boron-containing precursor”; ¶0032; “the silicon-containing precursor includes a silane compound, an organosilane compound, an alkyl silane compound, an alkoxy silane compound, a silanol compound, a siloxane compound, an aminosilane compound, a cyclic azasilane compound, a halosilane compound, or an inorganic silane compound”) and a metal-containing precursor (¶0029; ¶0230), wherein the silicon-containing precursor and the metal-containing precursor are provided through a showerhead (¶0279), and wherein a substrate (Fig. 1; 111; ¶0139) is housed within the processing region (¶0026 quoted above);
generating plasma effluents of the deposition precursors (as described in ¶0005, ¶0013, ¶0147, ¶0161-¶0162, ¶0170, ¶0174), wherein plasma effluents of the deposition precursors are generated at a plasma power of greater than or about 200 W (200W-800W ¶0177); and
forming a layer of silicon-and-metal-containing material (Fig. 1; the Mo and Si containing layer 113; ¶0230) on the substrate (111).
D1 is silent regarding wherein the showerhead is a dual channel showerhead to fluidly isolate the silicon-containing precursor and the metal-containing precursor prior to reaching the processing region.
In the same semiconductor field of endeavor, D5 teaches a semiconductor processing device comprising fully and fluidly isolating two precursors via a dual-channel showerhead and preventing contact between the precursors until they are delivered into the substrate processing region (D5; ¶0022, ¶0026, ¶0051) of a CVD chamber (as in D1; ¶0007).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual channel showerhead configuration of D5 for the showerhead of D1 in the method of D1. One of ordinary skill in the art would have motivation to do so in order to prevent the precursors of the method of D1 from contacting one another prematurely and reacting before reaching the substrate processing area (D5; ¶0026).
Regarding Claim 13, modified D1 teaches the semiconductor processing method of claim 12, wherein plasma effluents of the deposition precursors are generated at a plasma power of less than or about 2,000 W (200W-800W; D1 ¶0177).
Regarding Claim 14, modified D1 teaches the semiconductor processing method of claim 12, wherein the layer of silicon-and-metal-containing material is free of fluorine, oxygen, or both (contains 0% F; D1; ¶0036).
Regarding Claim 15, modified D1 teaches the semiconductor processing method of claim 12, further comprising: prior to providing the deposition precursors, pre-treating the substrate and forming a seed layer on the substrate (as described in D1 ¶0151, the pre-treatment can come before depositing the interfacial growth layer; D1; ¶0009; an interfacial growth layer if formed on the substrate before providing the deposition precursors).
Regarding Claim 16, modified D1 teaches the semiconductor processing method of claim 12, wherein a temperature within the processing region is maintained at less than or about 600 °C (D1; ¶0189; between 250 and 550 C).
Regarding Claim 17, modified D1 teaches the semiconductor processing method of claim 12, wherein a pressure within the processing region is maintained at less than or about 50 Torr (D1; ¶0189; between 20-40 Torr).
Regarding Claim 18, D1 teaches a semiconductor processing method comprising:
providing a silicon-containing precursor to a processing region of a semiconductor processing chamber (¶0006; “providing a substrate on a substrate holder in a processing chamber; exposing a top surface portion of the substrate to a metal-containing precursor (e.g., a Mo-containing precursor) and one or more optional deposition precursors”; ¶0030; “In any embodiment herein, the one or more deposition precursors is selected from the group consisting of a carbon-containing precursor, a silicon-containing precursor, and a boron-containing precursor”; ¶0032; “the silicon-containing precursor includes a silane compound, an organosilane compound, an alkyl silane compound, an alkoxy silane compound, a silanol compound, a siloxane compound, an aminosilane compound, a cyclic azasilane compound, a halosilane compound, or an inorganic silane compound”) through a showerhead (¶0278), wherein a substrate (Fig. 1; 111; ¶0139) is housed within the processing region (¶0026 “cause exposure of a top surface portion of a substrate to a Mo-containing precursor and one or more deposition precursors within the processing chamber”);
providing a metal-containing precursor to the processing region of the semiconductor processing chamber (¶0006; “providing a substrate on a substrate holder in a processing chamber; exposing a top surface portion of the substrate to a metal-containing precursor (e.g., a Mo-containing precursor) and one or more optional deposition precursors”) through the showerhead (¶0278),
generating plasma effluents of the deposition precursors (as described in ¶0005, ¶0013, ¶0147, ¶0161-¶0162, ¶0170, ¶0174); and
forming a layer of silicon-and-metal-containing material (Fig. 1; the Mo and Si containing layer 113; ¶0230) on the substrate (111), wherein the layer of silicon-and-metal-containing material is characterized by a metal concentration of greater than or about 20 at.% (up to 65% Mo; ¶0038).
D1 is silent regarding the details of the showerhead, wherein the silicon-containing precursor is provided through a first channel of a dual channel showerhead, and the metal-containing precursor is provided to the processing region of the semiconductor processing chamber through a second channel of the dual channel showerhead, wherein the first channel and the second channel are fluidly isolated.
In the same field of endeavor, D5 teaches a semiconductor processing device comprising fully and fluidly isolating two precursors via a dual-channel showerhead and preventing contact between the precursors until they are delivered into the substrate processing region (D5; ¶0022, ¶0026, ¶0051) of a CVD chamber (as in D1; ¶0007).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the dual channel showerhead configuration of D5 for the showerhead of D1 in the method of D1, fully isolating the metal-containing precursor through one channel of the dual showerhead and the silicon-containing precursor through the second channel of the dual showerhead until reaching the processing chamber. One of ordinary skill in the art would have motivation to do so in order to prevent the precursors of the method of D1 from contacting one another prematurely and reacting before reaching the substrate processing area (D5; ¶0026).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D5 and Takahiro Yokohama et al. (US 20240162047 A1; hereinafter D6).
Regarding Claim 19, modified D1 teaches the semiconductor processing method of claim 18, wherein the silicon-containing precursor comprises silane (SiH4) (D1; ¶0230).
D1 does not expressly disclose wherein the metal-containing precursor comprises tungsten hexafluoride (WF6).
In the same field of endeavor, D6 teaches forming a hardmask (103) for a semiconductor device and exemplifies the equivalence of molybdenum silicide and tungsten silicide as both suitable materials for such hardmask (D6; ¶0035; ¶0040). D6 discloses forming the equivalent tungsten silicide comprises utilizing WF6 (D6; ¶0039) and the resulting mask 103 also containing a non-metallic element silicon (D6; ¶0035).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the WF6 of D6 to replace the molybdenum precursor of D6 and combined with the SiH4 (of D6) to result in a tungsten and silicon containing hardmask 103 (of D6). One of ordinary skill in the art would recognize the equivalence of molybdenum and tungsten silicides for their intended purpose of being a hardmask in a semiconductor device (D6; ¶0035).
The substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.) See MPEP 2144.07.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D5 and Peter J. Gaczi (US 4766006 A; hereinafter D7).
Regarding Claim 20, modified D1 teaches the semiconductor processing method of claim 18, but is silent about the growth rates : wherein the layer of silicon-and-metal-containing material is formed at a rate of greater than or about 500 A/m.
D1 describes in ¶0173 “During deposition, one or more changes to one or more parameters such as pressure, flow rate, and temperature, may be used.” In the same field of endeavor, D7 teaches in Fig. 1 (D7; C3:L25-31; “Si/Mo and depostion rate (angstroms/min) versus deposition temperature. Deposition conditions: 0.25 torr, 4.3 sccm MoF.sub.6, 100 sccm SiH.sub.4.”) that the deposition rate of a metal (Mo) and silicon (Si) containing film depends on the temperature, and as shown by the line with triangle designation, the rate is over 500A/m.
PNG
media_image1.png
399
429
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to optimize the temperature (as in D7) to improve the growth rate of D1 to be over 500A/m in order to reduce manufacturing time. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Furthermore, the claimed range has not been established as critical. “Applicants should compare a sufficient number of tests both inside and outside the claimed range to show the criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197 (CCPA 1960). MPEP 716.02 (d) II.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN PRIDEMORE whose telephone number is (703)756-4640. The examiner can normally be reached Monday - Friday 8:00am - 4:00pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JULIO MALDONADO can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898