DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner acknowledges that in the response filed 12/30/2025 claims 1-26 were cancelled and claims 31-34 were added.
Election/Restrictions
Applicant’s election without traverse of Group III, Species IV (claims 27-34) in the reply filed on 12/30/2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement filed 5/16/2023 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered, specifically regarding the Search Report and Written Opinion dated 09-January-2023.
Claim Objections
Claim 28 is objected to because of the following informalities: in line 2, "progressively the" should be amended to read -progressively from the-. Appropriate correction is required.
Claim 30 is objected to because of the following informalities: in line 1, "comprising" should be amended to read -further comprising-. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 27-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nishihori et al (US 2016/0204213 and Nishihori hereinafter).
As to claims 27-29: Nishihori discloses [claim 27] a method of manufacturing a transistor (Figs. 3A-5C), comprising: depositing a gate insulator layer (Fig. 3A; 41; [0051]) of a thickness e1 (6 nm; [0051]) on an upper surface (top surface) of a semiconductor layer (SOI comprising 20 and 30; [0051]); forming a conductive gate (Fig. 3A; G; [0052]) on top of and in contact with a portion of the gate insulator layer (41); and thermally oxidizing (Fig. 3B; oxidization process; [0045]) the gate insulator layer (41) so that the gate insulator layer reaches a thickness e2 (in regions 42s and 42d; [0053]), greater than the thickness e1 (as shown, 42s and 42d are thicker than original thickness of 41), at locations below edge regions of the conductive gate (G) and remains at the thickness e1 at a location below a center of the conductive gate (G); [claim 28] wherein a thickness of the gate insulator (Fig. 3B; comprising 41, 42s, and 42d) varies progressively the thickness e1 to the thickness e2 (thickness from 41 original thickness to outer edge of 42s/42d is interpreted to be progressive) between the location below a center of the conductive gate (41 with original thickness of 41) and the locations below edge regions of the conductive gate (outer edges of 42s and 42d); [claim 29] wherein a difference between the thickness e1 and the thickness e2 is greater than or equal to 2 nm (Fig. 5B or 5C; e1 is 6 nm and e2 can be 9 nm or 12 nm where the difference is either 3 nm or 6 nm, both of which are greater than e1 of 6 nm; [0059]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 30-34 are rejected under 35 U.S.C. 103 as being unpatentable over Nishihori in view of Winstead et al (US 7,985,649 and Winstead hereinafter).
As to claims 30-34: Although the method disclosed by Nishihori shows substantial features of the claimed invention (discussed in paragraph 11 above), it fails to expressly disclose:
[claim 30] comprising: removing the gate insulator layer over a width L3 at location below extreme edge regions of the conductive gate; and depositing a layer of a low dielectric constant material under the extreme edges of the conductive gate; [claim 31] wherein removing the gate insulator layer further comprises removing oxide material from sides of the conductive gate; [claim 32] wherein depositing a layer of a low dielectric constant material further coats the sides of the conductive gate; [claim 33] wherein the layer of the low dielectric constant material coating the sides of the conductive gate forms an offset spacer for the conductive gate; [claim 34] wherein the width L3 is between 5% and 25% of a length of the conductive gate.
Nishihori discloses a method of forming a transistor with a thermally oxidized gate electrode and dielectric layer that forms a thicker region under the end regions of the gate electrode and a spacer on the sidewall of the gate electrode.
Winstead discloses forming a transistor where the oxidized portion under the gate electrode (analogous to 42s and 42d of Nishihori) and on the sidewall of the transistor (analogous to 43 of Nishihori) is removed such that the method [claim 30] comprising: removing the gate insulator layer (Figs. 4-5; 22 in 20 and on sidewall of gate electrode 16 is removed; col. 2, lines 64-67 and col. 3, lines 1-8) over a width L3 (undercut region 20; col. 2, lines 37-50 and col. 3, lines 3-8) at location below extreme edge regions (region 20) of the conductive gate (16); and depositing a layer (Fig. 6; 28; col. 3, lines 9-17) of a low dielectric constant material (28 is grown using silicon as the substrate material and polysilicon as the conductive gate and thus can be silicon oxide, which is interpreted to be a low dielectric constant material as it is lower than a high-k dielectric material; col. 2, lines 13-36) under the extreme edges (region 20) of the conductive gate (16); [claim 31] wherein removing the gate insulator layer (Figs. 4-5; 22 in 20 and on sidewall of gate electrode 16 is removed; col. 2, lines 64-67 and col. 3, lines 1-8) further comprises removing oxide material (22) from sides (sidewalls) of the conductive gate (16); [claim 32] wherein depositing a layer of a low dielectric constant material (Fig. 6; 28 is grown using silicon as the substrate material and polysilicon as the conductive gate and thus can be silicon oxide, which is interpreted to be a low dielectric constant material as it is lower than a high-k dielectric material; col. 2, lines 13-36 and col. 3, lines 9-17) further coats (with 28) the sides (sidewalls) of the conductive gate (16).
As to [claim 33] wherein the layer of the low dielectric constant material coating the sides of the conductive gate forms an offset spacer for the conductive gate, when the process of replacing the oxidized region of the gate electrode and sidewall of the gate electrode (22 in Winstead and 42s, 42d, and 43 in Nishihori) and then the low dielectric constant material 28 formed under and on the sidewalls of the gate electrode 16 of Winstead is modified to remove 42s, 42d, and 43 (the oxidized portions) of Nishihori and then replaced with layer 28 of Winstead, Nishorihi will have Fig. 4A 42s, 42d, and 43 replaced with 28 of Winstead such that spacer 50 of Nishihori is formed on 28 Winstead in Nishihori. As shown in Fig. 4B of Nishihori, the layer 43 (which will be 28 using the modification of Winstead) and 50 are used as an offset spacer to form the source/drain regions. Therefore, the layer of low dielectric constant 28 will be used in part as the offset spacer (in combination with 50).
Therefore, a person having ordinary skill in the art would before the effective filing date of the claimed invention would have had it within their ordinary capabilities to remove an oxidized region of the gate electrode (which is 42s and 42d as well as the sidewall portion 43) of Nishiori because the technique was well known in the art in view of the teaching of Winstead using the technique in another device and the use of which in Nishihori would have resulted in the predictable results of reducing the electric field at the corner of the gate electrode (col. 1, line 67 and col. 2, lines 1-4 of Winstead).
As to [claim 34] wherein the width L3 is between 5% and 25% of a length of the conductive gate, when the oxidized portion of Nishihori (which is 42s and 42d) are removed using the process of removing what is oxidized in region 20 of Winstead, portions of the gate dielectric in the gate length of 100 nm to 300 nm will be removed (see [0036] of Nishihori). Figs. 5B and 5C of Nishihori disclose that the region to be removed using the modification of Winstead would be Lbp (from the edge of the gate electrode to the edge of original thickness of gate dielectric), which can be 10 nm or 13 nm, see also [0061], which is in a range of approximately 3% and 13% of the gate length (when the gate length is 100 nm to 300 nm). Therefore, the claimed range and the disclosed range overlaps in scope. As stated in MPEP 2144.05(I), “[i]n the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) (The prior art taught carbon monoxide concentrations of "about 1-5%" while the claim was limited to "more than 5%." The court held that "about 1-5%" allowed for concentrations slightly above 5% thus the ranges overlapped.); In re Geisler, 116 F.3d 1465, 1469-71, 43 USPQ2d 1362, 1365-66 (Fed. Cir. 1997) (Claim reciting thickness of a protective layer as falling within a range of "50 to 100 Angstroms" considered prima facie obvious in view of prior art reference teaching that "for suitable protection, the thickness of the protective layer should be not less than about 10 nm [i.e., 100 Angstroms]." The court stated that "by stating that ‘suitable protection’ is provided if the protective layer is ‘about’ 100 Angstroms thick, [the prior art reference] directly teaches the use of a thickness within [applicant’s] claimed range."). See also In re Bergen, 120 F.2d 329, 332, 49 USPQ 749, 751-52 (CCPA 1941) (The court found that the overlapping endpoint of the prior art and claimed range was sufficient to support an obviousness rejection, particularly when there was no showing of criticality of the claimed range).” Further, given that Nishihori discloses that the extent of the thickness of the oxidized portion formed originally (42s and 42d) that will be removed (in region Lbp) using the method of Winstead is a result effective variable as it affects the on-resistance and on-state breakdown voltage of the device (see [0064] of Nishihori), it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to choose the gate length and/or the thickness of the bird peak regions (42s and 42d) that results in a length of a bird peak Lbp that is removed that is within the claimed range of 5% to 25% of the gate length given that the Lbp and bird peak thickness are result effective variables that would be modified to balance the desired level of on-resistance and on-state breakdown voltage while not making it too thick to make the performance of the transistor undesirable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
1/23/2026