DETAILED ACTION
This Office action is in response to the election filed on 03 October 2025. Claims 1-12 and 21-28 are pending in the application. Claims 13-20 have been cancelled. Claims 21-28 are newly submitted.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I, on which claims 1-12 and 21-28 are readable, in the reply filed on 03 October 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 21, 25, 26, and 27 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Basker et al., US 9,613,954.
With respect to independent claim 1, Basker et al. disclose a method for forming a semiconductor device, shown in Figs. 12A/12B-18A/18B, comprising:
performing a first etching process to define a plurality of fins 30 and a corresponding plurality of device isolation structures on a substrate 10 (see Fig. 12B below), see column 5, lines 29-67, bridging column 6 to line 19 (In column 5, lines 63-67, bridging column 6 to line 4, Basker teaches that a dielectric cap can be patterned by an anisotropic etch to define the plurality of underlying fins 30.);
forming an enhancement layer 40 on each of the plurality of fins 30, the enhancement layer 40 encapsulating each of the plurality of fins 30, see Fig. 12B and column 12, lines 34-67;
performing a second etching process to remove at least one fin 30 of the plurality of fins 30, see Figs. 15B and 16B and column 14, lines 65-67, bridging column 15 to line 15;
performing a third etching process to remove at least a portion of the enhancement layer 40, see Figs. 14B and 15B and column 14, lines 33-64;
depositing an STI material 14 on the plurality of fins 30 and the corresponding plurality of device isolation structures (see annotated Fig. 12B below for device isolation structures), see column 15, lines 16-45; and
recessing the plurality of fins 30 relative to the STI material 14, see Fig. 17B and column 15, lines 16-45;
PNG
media_image1.png
581
815
media_image1.png
Greyscale
.
With respect to claim 2, in the method of Basker et al., the enhancement layer 40 comprises at least one of an oxide or a nitride, see column 12, lines 50-52.
With respect to claim 3, in the method of Basker et al., the enhancement layer 40 is a silicon nitride.
With respect to claim 5, the method of Basker et al. further comprises forming a gate oxide component 50 on at least one of the plurality of fins 30, see Fig. 18B; column 11, lines 1-20; and column 15, lines 46-51. Since Basker et al. disclose that enhancement layer 40 can comprise an oxide (see column 12, lines 50-51), and since gate component 50 is in contact with enhancement layer 40, as shown in Fig. 18B, layer 50 meets the limitation of “a gate oxide component’, within the scope of claim 26.
With respect to claim 6, the method of Basker et al. further comprises forming a gate structure 52 on the gate oxide component 50, see Fig. 18B and column 11, lines 1-20.
With respect to independent claim 21, Basker et al. disclose a method for forming a semiconductor device, shown in Figs. 12A/12B-18A/18B, comprising:
forming an enhancement layer 40 on each fin 30 in a plurality of fins 30 on a substrate 10, see Fig. 12B and column 12, lines 34-67;
removing at least one fin 30 of the plurality of fins 30, see Figs. 15B and 16B and column 14, lines 65-67, bridging column 15 to line 15;
removing at least a portion of the enhancement layer 40, see Figs. 14B and 15B and column 14, lines 33-64;
depositing an STI material 14 on the plurality of fins 30, see column 15, lines 16-45; and
removing a portion of the STI material 14 to expose the plurality of fins 30, see Fig. 17B and column 15, lines 16-45.
With respect to claim 25, in the method of Basker et al., the enhancement layer 40 is a silicon nitride, see column 12, lines 50-52.
With respect to claim 26, Basker et al. disclose a method for forming a semiconductor device, shown in Figs. 12A/12B-18A/18B, comprising:
performing a first etching process to define a plurality of fins 30 and a corresponding plurality of device isolation structures on a substrate 10 (see Fig. 12B below), see column 5, lines 29-67, bridging column 6 to line 19 (In column 5, lines 63-67, bridging column 6 to line 4, Basker teaches that a dielectric cap can be patterned by an anisotropic etch to define the plurality of underlying fins 30.);
forming an enhancement layer 40 on each of the plurality of fins 30, the enhancement layer 40 encapsulating each of the plurality of fins 30, see Fig. 12B and column 12, lines 34-67;
performing a second etching process to remove at least one fin 30 of the plurality of fins 30, see Figs. 15B and 16B and column 14, lines 65-67, bridging column 15 to line 15;
performing a third etching process to remove at least a portion of the enhancement layer 40, see Figs. 14B and 15B and column 14, lines 33-64;
depositing an STI material 14 on the plurality of fins 30 and the corresponding plurality of device isolation structures (see annotated Fig. 12B below for device isolation structures), see column 15, lines 16-45; and
recessing the plurality of fins 30 relative to the STI material 14. see Fig. 17B and column 15, lines 16-45;
forming a gate oxide component 50 on at least one of the plurality of fins 30, see Fig. 18B; column 11, lines 1-20; and column 15, lines 46-51 (Since Basker et al. disclose that enhancement layer 40 can comprise an oxide (see column 12, lines 50-51), and since gate component 50 is in contact with enhancement layer 40, as shown in Fig. 18B, layer 50 meets the limitation of “a gate oxide component’, within the scope of claim 26.); and
forming a gate structure 52 on the gate oxide component 50, see Fig. 18B and column 11, lines 1-20.
PNG
media_image1.png
581
815
media_image1.png
Greyscale
With respect to claim 27, in the method of Basker et al., the enhancement layer 40 comprises an oxide or a nitride, see column 12, lines 50-52.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al., US 9,613,954, as applied to claims 1 and 21 above, in view of Cho et al., JP 2009-246332.
With respect to claim 7, Basker et al. is applied as above. However, although Basker et al. disclose forming a plurality of fins 30, Basker et al. do not disclose prior to performing the first etching process, depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; and patterning a photoresist on the hard mask layer, wherein the first etching process is performed in accordance with the patterned photoresist. In the same field of endeavor, Cho et al. disclose a method of forming a plurality of fins on a substrate 100, as shown in Figs. 2A-2G. The etching process of Cho et al. comprises, prior to etching to form the plurality of fins, depositing a pad layer 210 on the substrate 100, depositing a first insulative layer 212 on the pad layer 210 (Cho et al. disclose: “Referring to FIG. 2A, a pad oxide film 210 and a nitride film 212 are sequentially formed in the high density pattern region A and the low density pattern region B on the substrate 100, respectively.”); depositing a hard mask layer 120/130 on the first insulative layer 212 (Cho et al. disclose: “the first hard mask layer 120, the second hard mask layer 130”), and patterning a photoresist 144 on the hard mask layer 120/130 (Cho et al. disclose: “A photoresist pattern 144 is formed on the antireflection film 142 in the high-density pattern region A.”), as shown in Fig. 2A. An etching process is then performed in accordance with the patterned photoresist 144, as shown in Figs. 2B-2F. Since the etching process of Cho et al. yields a fine pattern of semiconductor fins, as shown in Fig. 2F of Cho et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Cho et al. in the known method of Basker et al. to form the plurality of fins 30.
With respect to claim 22, Basker et al. is applied as above. However, although Basker et al. disclose forming a plurality of fins 30, Basker et al. do not disclose the plurality of fins is formed by: depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; patterning a photoresist on the hard mask layer; and performing a first etching process to form the plurality of fins and a corresponding plurality of device isolation structures on the substrate. In the same field of endeavor, Cho et al. disclose a method of forming a plurality of fins on a substrate 100, as shown in Figs. 2A-2G. The etching process of Cho et al. comprises, prior to etching to form the plurality of fins, depositing a pad layer 210 on the substrate 100, depositing a first insulative layer 212 on the pad layer 210 (Cho et al. disclose: “Referring to FIG. 2A, a pad oxide film 210 and a nitride film 212 are sequentially formed in the high density pattern region A and the low density pattern region B on the substrate 100, respectively.”); depositing a hard mask layer 120/130 on the first insulative layer 212 (Cho et al. disclose: “the first hard mask layer 120, the second hard mask layer 130”), and patterning a photoresist 144 on the hard mask layer 120/130 (Cho et al. disclose: “A photoresist pattern 144 is formed on the antireflection film 142 in the high-density pattern region A.”), as shown in Fig. 2A. Cho et al. then teach performing an etching process to form a plurality of fins 260a and a corresponding plurality of device isolation structures (the space separating adjacent fins 260a) on the substrate 100, as shown in Figs. 2B-2F. Since the etching process of Cho et al. yields a fine pattern of semiconductor fins, as shown in Fig. 2F of Cho et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Cho et al. in the known method of Basker et al. to form the plurality of fins 30.
With respect to claim 23, in the etching process of Cho et al., the hard mask layer 120/130 is removed prior to depositing the STI material 270, see Figs. 2C-2G.
With respect to claim 24, in the combination of Basker et al. and Cho et al., after depositing the STI material 14 and removing a portion of the STI material 14 in the known of Basker et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to expose the first insulative layer 212; to remove the first insulative layer 212; and to remove the pad layer, thereby exposing the fins and enabling the gate component 50 and gate structure 52 to make electrical contact with the active regions 30 of the transistors, as shown in Fig. 18B of Basker et al.
Claims 7, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al., US 9,613,954, as applied to claims 1 and 21 above, in view of Kim, 10-2006-0011612.
With respect to claim 7, Basker et al. is applied as above. However, although Basker et al. disclose forming a plurality of fins 30, Basker et al. do not disclose prior to performing the first etching process, depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; and patterning a photoresist on the hard mask layer, wherein the first etching process is performed in accordance with the patterned photoresist. In the same field of endeavor, Kim discloses a method of forming a plurality of fins on a substrate 100, as shown in Figs. 3a-3f. The etching process of Kim comprises, prior to etching to form the plurality of fins, depositing a pad layer 22 on the substrate 21, depositing a first insulative layer 23 on the pad layer 22; depositing a hard mask layer 24 on the first insulative layer 23, and patterning a photoresist 25 on the hard mask layer 24, as shown in Fig. 3a. An etching process is then performed in accordance with the patterned photoresist 25, as shown in Figs. 3b-3c. Since the etching process of Kim yields a fine pattern of semiconductor fins, as shown in Fig. 3c of Kim, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Kim in the known method of Basker et al. to form the plurality of fins 30.
With respect to claim 22, Basker et al. is applied as above. However, although Basker et al. disclose forming a plurality of fins 30, Basker et al. do not disclose the plurality of fins is formed by: depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; patterning a photoresist on the hard mask layer; and performing a first etching process to form the plurality of fins and a corresponding plurality of device isolation structures on the substrate. In the same field of endeavor, Kim discloses a method of forming a plurality of fins on a substrate 21, as shown in Figs. 3a-3f. The etching process of Kim comprises, prior to etching to form the plurality of fins, depositing a pad layer 22 on the substrate 21, depositing a first insulative layer 23 on the pad layer 22; depositing a hard mask layer 24 on the first insulative layer 23; and patterning a photoresist 25 on the hard mask layer 24, as shown in Fig. 3a. Kim then teaches performing an etching process to form a plurality of fins 21 and a corresponding plurality of device isolation structures (the space separating adjacent fins 21) on the substrate 21, as shown in Figs. 3b-3c. Since the etching process of Kim. yields a fine pattern of semiconductor fins, as shown in Fig. 3c of Kim., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Kim in the known method of Basker et al. to form the plurality of fins 30.
With respect to claim 24, in the etching process of Kim, after depositing the STI material 27, exposing the first insulative layer 23, as shown in Figs. 3d and 3e of Cho, removing the first insulative layer 23, and removing the pad layer 22, as shown in Fig. 3f of Kim.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al., US 9,613,954, in view of Kim, 10-2006-0011612, as applied to claim 7 above, further in view of Cai et al., US 2013/0200468, and Huang et al, US 2015/0093877.
With respect to claim 8, Basker et al. and Kim are applied as above. However, none of these references teach or suggest that a chemical mechanical polish process can be performed to remove the hard mask layer prior to depositing the STI material. Both Cai et al. and Huang et al. disclose removing a hard mask layer prior to depositing STI material. In the method of Cai et al., Cai et al. teach that as shown in Fig. 2A after patterning the plurality of fins 202, any remaining hard mask (not shown) can be removed by chemical mechanical polishing, see paragraph [0033] and Fig. 2A. Since Cai et al. do not show the hard mask layer, Huang et al. has been additionally relied upon, since Huang et al. clearly shows the removal of a hard mask layer 208 prior to depositing STI material 214, as shown in Figs. 2A-2D, see paragraphs [0032]-[0039]. In light of both Cai et al. and Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the hard mask layer in the method of Kim could have been removed by chemical mechanical polishing prior to depositing the STI material.
With respect to claim 9, performing the chemical mechanical polish process of Cai et al. in the known method of Kim would expose the first insulative layer 23 underlying the hard mask layer 24.
With respect to claim 10, both Cai et al. and Huang et al. disclose performing a fourth etching process to remove a portion of the STI material, see paragraph [0039] of Cai et al. and see Fig. 2D and paragraph [0038] of Huang et al.
With respect to claim 11, Kim discloses performing a fifth etching process to remove the first insulative layer 23. Kim discloses that the pad nitride layer 23 and the first pad oxide film 22 is removed, optionally to form a device isolation film (27a).
With respect to claim 12, Kim discloses performing a sixth etching process to remove the pad layer 22. Kim discloses that the pad nitride layer 23 and the first pad oxide film 22 is removed, optionally to form a device isolation film (27a).
Claims 4 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Basker et al., US 9,613,954, as applied to claims 3 and 26 above.
With respect to claims 4 and 28, in the method of Basker et al., the enhancement layer 40 is deposited in the range of about 1 angstrom to 35 angstroms, see column 12, lines 44-67. Basker et al. disclose a thickness in the range of 5 nm to 100 nm, but teaches that lesser and greater thicknesses can also be employed, see column 12, lines 64-67. In light of this teaching of Basker et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a thickness less than 50 angstroms could have been employed in the known method of Basker et al. Furthermore, arguably, a thickness of about 35 angstroms would have been obvious in light of the teaching of Basker et al. of a thickness of 50 angstroms.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 and 26-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 5 and 26 requires “a gate oxide component”. It is unclear if this terminology, that is, “a gate oxide component”, requires the gate component to comprise oxide.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose methods of fabricating finFETs in which at least one fin of a plurality of fins is removed and a STI material is deposited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898