DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) filed on 05 August 2026. Claims 1-12 and 21-28 are pending in the application. Claims 13-20 have been cancelled.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species I, on which claims 1-12 and 21-28 are readable, in the reply filed on 03 October 2025 is acknowledged.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 15 July 2026 has been entered.
Allowable Subject Matter
The indicated allowability of claims 26-28 is withdrawn in view of the newly discovered reference to Hu et al., US 2018/0308746. Rejections based on the newly cited reference follow.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 21 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Hu et al., US 2018/0308746, newly cited.
With respect to claim 1, Hu et al. disclose a method for forming a semiconductor device, shown in Figs. 2-11, comprising:
performing a first etching process to define a plurality of fins 110 and a corresponding plurality of device isolation structures 200 on a substrate 100, see Fig. 2 and paragraphs [0024]-[0038];
forming an enhancement layer 300 on each of the plurality of fins 110, the enhancement layer 300 encapsulating each of the plurality of fins 110, see Fig. 3 and paragraphs [0039]-[0044];
depositing and patterning a photoresist layer 330 over the substrate 100 to define a covered portion and an uncovered portion, the uncovered portion including at least one fin 110 of the plurality of fins 110, see Fig. 4 and paragraphs [0045]-[0059];
performing a second etching process to remove the at least one fin 110 of the plurality of fins 110 and a portion of the enhancement layer 300 encapsulating the at least one fin 110 in the uncovered portion, see Fig. 5 and paragraphs [0061]-[0063];
removing the photoresist layer 330, see paragraph [0060];
performing a third etching process to remove at least a portion of the enhancement layer 300 encapsulating the plurality of fins 110 previously in the covered portion, see Fig. 8 and paragraphs [0075]-[0077];
after performing the third etching process, depositing an STI material 150 on the plurality of fins 110 and the corresponding plurality of device isolation structures200, as shown in Fig. 10; and
recessing the plurality of fins 110 relative to the STI material 150, see Fig. 11 and paragraphs [0086]-[0088].
With respect to claim 2, in the method of Hu et al., the enhancement layer comprises at least one of an oxide or a nitride, see paragraph [0041].
With respect to claim 21, Hu et al. disclose a method for forming a semiconductor device, shown in Figs. 2-11 comprising:
forming an enhancement layer 300 on each fin 110 in a plurality of fins on a substrate 100, the substrate 100 also including a corresponding plurality of device isolation structures 200, as shown in Figs. 2 and 3;
removing at least one fin 110 of the plurality of fins and the enhancement layer 300 encapsulating the at least one fin 110, as shown in Figs. 3 and 5;
removing at least a portion of the enhancement layer 300 encapsulating sidewalls, tops, fronts, and backs of the plurality of fins 110, see Fig. 8 and paragraphs [0075]-[0077];
after removing at least a portion of the enhancement layer 300, depositing an STI material 150 on the plurality of fins 110 and the corresponding plurality of device isolation structures 200, as shown in Fig. 10; and
removing a portion of the STI material 150 to expose the plurality of fins 110; and recessing the plurality of fins relative to the STI material 150, see Fig. 11 and paragraphs [0086]-[0088].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al., US 2018/0308746, newly cited, in view of Basker et al., US 9,613,954, of record.
With respect to claim 26, Hu et al. disclose a method for forming a semiconductor device, shown in Figs. 2-11, comprising:
performing a first etching process to define a plurality of fins 110 and a corresponding plurality of device isolation structures 200 on a substrate 100, see Fig. 2 and paragraphs [0024]-[0038];
forming an enhancement layer 300 on each of the plurality of fins 110, the enhancement layer 300 encapsulating each of the plurality of fins 110, see Fig. 3 and paragraphs [0039]-[0044];
depositing and patterning a photoresist layer 330 over the substrate 100 to define a covered portion and an uncovered portion, the uncovered portion including at least one fin 110 of the plurality of fins 110, see Fig. 4 and paragraphs [0045]-[0059];
performing a second etching process to remove the at least one fin 110 of the plurality of fins 110 and a portion of the enhancement layer 300 in the uncovered portion, see Fig. 5 and paragraphs [0061]-[0063];
removing the photoresist layer 330, see paragraph [0060];
performing a third etching process to remove at least a portion of the enhancement layer 300 previously in the covered portion, see Fig. 8 and paragraphs [0075]-[0077];
after performing the third etching process, depositing an STI material 150 on the plurality of fins 110 and the corresponding plurality of device isolation structures 200, as shown in Fig. 10; and
recessing the plurality of fins 110 relative to the STI material 150, see Fig. 11 and paragraphs [0086]-[0088]. Although Hu et al. disclose substrate 100 may provide a platform for forming fin field effect transistors (FinFETs) (paragraph [0025]) and that in a FinFET, a gate structure controls the fin from two sides of the fin (paragraph [0004]), Hu et al. fail to specifically disclose forming a gate dielectric on at least one of the plurality of fins and forming a gate structure on the gate dielectric. In the same field of endeavor, Basker et al. disclose forming a gate dielectric 50 on at least one of the plurality of fins 30, see Fig. 18B; column 11, lines 1-20; and column 15, lines 46-51, and forming a gate structure 52 on the gate dielectric 50, see Fig. 18B and column 11, lines 1-20. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gate dielectric layer and a gate structure in the known method of Hu et al. in order to form an operable FinFET.
With respect to claim 27, in the method of Hu et al., the enhancement layer comprises an oxide or a nitride, see paragraph [0041].
With respect to claim 28, Hu et al. disclose the enhancement layer 300 is deposited in the range of about 1 angstrom to 35 angstroms, see paragraph [0044].
Claims 3-6 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al., US 2018/0308746, newly cited, as applied to claims 1 and 21 above, in view of Basker et al., US 9,613,954, of record.
Hu et al. is applied as above. Hu et al. lack anticipation of the enhancement layer being a silicon nitride layer, as required in dependent claims 3 and 25. In the same field of endeavor, Basker et al. disclose a method in which an enhancement layer 40 is formed on each of the plurality of fins 30, the enhancement layer 40 encapsulating each of the plurality of fins 30, see Fig. 12B and column 12, lines 34-67 prior to removing at least one fin 30 of a plurality of fins 30 and the enhancement layer 40, see Figs. 15B and 16B and column 14, lines 65-67, bridging column 15 to line 15. Basker et al. disclose the enhancement layer 40 can comprises at least one of an oxide or a nitride, see column 12, lines 50-59. Since Basker et al. disclose the functional equivalence of silicon oxide and silicon nitride as the material of an enhancement layer, it would
been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the enhancement layer 300 could comprise a silicon nitride layer in the known method of Hu et al.
With respect to claim 4, Hu et al. disclose the enhancement layer 300 is deposited in the range of about 1 angstrom to 35 angstroms, see paragraph [0044] of Hu et al..
With respect to claims 5 and 6, although Hu et al. disclose substrate 100 may provide a platform for forming fin field effect transistors (FinFETs) (paragraph [0025]) and that in a FinFET, a gate structure controls the fin from two sides of the fin (paragraph [0004]), Hu et al. fail to specifically disclose forming a gate dielectric on at least one of the plurality of fins and forming a gate structure on the gate dielectric. In the same field of endeavor, Basker et al. disclose forming a gate dielectric 50 on at least one of the plurality of fins 30, see Fig. 18B; column 11, lines 1-20; and column 15, lines 46-51, and forming a gate structure 52 on the gate dielectric 50, see Fig. 18B and column 11, lines 1-20. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a gate dielectric layer and a gate structure in the known method of Hu et al. in order to form an operable FinFET.
Claims 7, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al., US 2018/0308746, newly cited, as applied to claims 1 and 21 above, in view of Kim, 10-2006-0011612, of record.
With respect to claim 7, Hu et al. is applied as above. However, although Hu et al. disclose forming the plurality of fins 110 using a hard mask layer (see paragraph 0018) and using fin hard mask layer 200 of silicon nitride (see paragraphs [0035]-[0037], Hu et al. do not disclose that forming the fin mask layer 200 comprises depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; and patterning a photoresist on the hard mask layer, wherein the first etching process is performed in accordance with the patterned photoresist. In the same field of endeavor, Kim discloses a method of forming a plurality of fins on a substrate 100, as shown in Figs. 3a-3f. The etching process of Kim comprises, prior to etching to form the plurality of fins, depositing a pad layer 22 on the substrate 21, depositing a first insulative layer 23 on the pad layer 22; depositing a hard mask layer 24 on the first insulative layer 23, and patterning a photoresist 25 on the hard mask layer 24, as shown in Fig. 3a. An etching process is then performed in accordance with the patterned photoresist 25, as shown in Figs. 3b-3c. Since the etching process of Kim yields a fine pattern of semiconductor fins, as shown in Fig. 3c of Kim, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Kim in the known method of Hu et al. to form the plurality of fins 110, thereby forming the fin mask layer 200 in the known method of Hu et al. comprising a pad layer 22, a first insulative layer 23 on the pad layer 22; and a hard mask layer 24 on the first insulative layer 23.
With respect to claim 22, Hu et al. is applied as above. However, although Hu et al. disclose forming the plurality of fins 110 using a hard mask layer (see paragraph 0018) and using fin hard mask layer 200 of silicon nitride (see paragraphs [0035]-[0037], Hu et al. do not disclose that forming the fin mask layer 200 comprises depositing a pad layer on the substrate; depositing a first insulative layer on the pad layer; depositing a hard mask layer on the first insulative layer; patterning a photoresist on the hard mask layer; and performing a first etching process to form the plurality of fins and a corresponding plurality of device isolation structures on the substrate. In the same field of endeavor, Kim discloses a method of forming a plurality of fins on a substrate 21, as shown in Figs. 3a-3f. The etching process of Kim comprises, prior to etching to form the plurality of fins, depositing a pad layer 22 on the substrate 21, depositing a first insulative layer 23 on the pad layer 22; depositing a hard mask layer 24 on the first insulative layer 23; and patterning a photoresist 25 on the hard mask layer 24, as shown in Fig. 3a. Kim then teaches performing an etching process to form a plurality of fins 21 and a corresponding plurality of device isolation structures (the space separating adjacent fins 21) on the substrate 21, as shown in Figs. 3b-3c. Since the etching process of Kim. yields a fine pattern of semiconductor fins, as shown in Fig. 3c of Kim., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the etching process of Kim in the known method of Hu et al. to form the plurality of fins 110, thereby forming the fin mask layer 200 in the known method of Hu et al. comprising a pad layer 22, a first insulative layer 23 on the pad layer 22; and a hard mask layer 24 on the first insulative layer 23.
Claim 22 requires the etched portions of the pad layer 22, the first insulative layer 23, and the hard mask layer 24 are present upon the plurality of fins and are also encapsulated by the enhancement layer. Hu et al. clearly show in Fig. 3 that fin mask layer is present upon the plurality of fins and is encapsulated by the enhancement layer 300. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to leave the etched portions of the pad layer 22, the first insulative layer 23, and the hard mask layer 24 present upon the plurality of fins and to encapsulate them with the enhancement layer 300, since this is taught by Hu et al.
With respect to claim 24, in the etching process of Kim, after depositing the STI material 27 and prior to recessing the plurality of fins, exposing the first insulative layer 23, as shown in Figs. 3d and 3e of Cho, removing the first insulative layer 23, and removing the pad layer 22, as shown in Fig. 3f of Kim.
Claims 8-12 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Hu et al., US 2018/0308746, newly cited, in view of Kim, 10-2006-0011612, of record, as applied to claim 7 above, further in view of Cai et al., US 2013/0200468, and Huang et al, US 2015/0093877, both of record.
Hu et al. and Kim are applied as above in the rejection of claim 7. Hu et al. disclose planarizing the STI material 150 by chemical mechanical polishing to expose the top surface of the mask layer 200, see paragraphs [0086]-[0088]. Hu et al. further disclose the mask layer 200 can be removed by performing an etching process, see paragraph [0089]. However, with respect to claim 8, the combination of Hu et al. and Kim fails to teach removing the hard mask prior to depositing the STI material by performing a chemical mechanical polish step, and with respect to claim 23, the combination of Hu et al. and Kim fails to teach removing the hard mask layer prior to depositing the STI material.
Both Cai et al. and Huang et al. disclose removing a hard mask layer prior to depositing STI material. In the method of Cai et al., Cai et al. teach that as shown in Fig. 2A after patterning the plurality of fins 202, any remaining hard mask (not shown) can be removed by chemical mechanical polishing, see paragraph [0033] and Fig. 2A. Since Cai et al. do not show the hard mask layer, Huang et al. has been additionally relied upon, since Huang et al. clearly shows the removal of a hard mask layer 208 prior to depositing STI material 214, as shown in Figs. 2A-2D, see paragraphs [0032]-[0039]. In light of both Cai et al. and Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the hard mask layer in the method of Kim could have been removed by chemical mechanical polishing prior to depositing the STI material.
With respect to claim 9, performing the chemical mechanical polish process of Cai et al. in the known method of Kim would expose the first insulative layer 23 underlying the hard mask layer 24.
With respect to claim 10, both Cai et al. and Huang et al. disclose performing a fourth etching process to remove a portion of the STI material, see paragraph [0039] of Cai et al. and see Fig. 2D and paragraph [0038] of Huang et al.
With respect to claim 11, Kim discloses performing a fifth etching process to remove the first insulative layer 23. Kim discloses that the pad nitride layer 23 and the first pad oxide film 22 are removed, optionally to form a device isolation film (27a).
With respect to claim 12, Kim discloses performing a sixth etching process to remove the pad layer 22. Kim discloses that the pad nitride layer 23 and the first pad oxide film 22 is removed, optionally to form a device isolation film (27a).
Response to Arguments
Applicant’s arguments with respect to claims 1-12 and 21-28 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various methods of fabricating a semiconductor device comprising a step of removing a portion of an enhancement layer and a fin.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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