Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 1/8/2026.
Claims 1-20 are currently pending.
Claims 19-20 have been withdrawn. 19 and 20 were submitted with incorrect claim status identifiers and were not marked as withdrawn with the claim status identifiers. The claim status of 19 and 20 should be corrected in the subsequent response. MPEP 714 II.C(A).
Claims 1-18 have been examined.
Election/Restriction
Applicant's election with traverse of 1-18 of Group I in the reply filed on 1/8/2026 is acknowledged. The traversal is on the grounds that no unreasonable search burden exists because “a search would likely yield a limited number of references for examination”. (Page 7 of Applicants Remarks in Response to Restriction submitted on 1/8/2026.) As stated previously in the requirement for restriction dated 12/02/2025, serious search and examination burden on the examiner is shown at least because each invention has a separate field of search, as shown by the different classification numbers that would need to be searched under. In this particular instant, searching for the method of making would employ different classes/subclasses (as noted in the restriction grouping), electronic resources, and search queries. This different search strategy can produce an unpredictably large quantity of references for the examiner. Therefore, the Applicant’s remarks are not found persuasive.
The requirement is still deemed proper and is therefore made FINAL.
Claims 19 and 20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/8/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/16/2023 and 9/6/2023, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-8, 10-11, 14 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Tak et al. US 20210066458 A1 (hereinafter Tak) in view of Goda et al. US 20210202751 A1 (hereinafter Goda) under the below first interpretation.
The Following annotated figure from Tak will be used in discussion.
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The following annotated figure from Goda will be used in discussion.
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Regarding claim 1, Tak discloses:
A three-dimensional memory device, (Fig. 5A, semiconductor device) comprising:
a plurality of alternating layers formed over a surface of a substrate, (Fig. 5A, [0076], conductive layer 51 and insulating layer 52 are stacked in the vertical direction on a substrate.) wherein the alternating layers comprises a word line layer (conductive layer 51) and an inter-word line dielectric layer (insulating layer 52) that are stacked in a first direction;
a gate coupled to each of the word line layers of the plurality of alternating layers; ([0075], the conductive layers 51 may be gate electrodes.)
a multi-layer channel (annotated Fig. 5A, multi-layer channel) … extending in the first direction between the source region and the drain region, (the multi-layer channel extends in the vertical direction) wherein the multi-layer channel comprises:
a first conductive layer extending between the source region and the drain region; (Fig. 5A, channel region 54)
… and
an ONO layer stack (memory layer 53) disposed between the gate (conductive layer 51) and the multi-layer channel(annotated Fig. 5A, multi-layer channel), wherein the ONO layer stack extends in the first direction between the source region and the drain region. (Fig. 5A, memory layer 53 extends in the vertical direction.)
While Tak does not directly discuss “a multi-layer channel (annotated Fig. 5A, multi-layer channel) having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region.” The device of Tak would need to have a source and drain in order to be a functioning device.
Furthermore, Goda, which teaches an apparatus for 3D NAND flash memory devices (Goda, [0022]), discloses:
a multi-layer channel (Annotated Fig. 2H, multi-layer channel.) having a first end coupled to a source region, ([0028], base conductive material is the source line.) a second end coupled to a drain region, ([0041], second plug material 124 being a drain contact) and extending in the first direction between the source region and the drain region, (Annotated Fig. 2H, multi-layer channel has a length in the vertical direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first end coupled to a source region, a second end coupled to a drain region, as taught by Goda in order to practice the invention of Tak.
Tak does not appear to disclose “a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer.”
Goda further discloses:
a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; and (Fig. 2H, second channel material 119. [0036], the second channel material is different than the first channel material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; as taught by Goda for purposes of improving reliability, lower leakage, and improve mobility. (Goda, [0039].)
Regarding claim 2, Tak and Goda disclose all the elements of claim 1.
Tak further discloses
wherein the first conductive layer comprises indium zinc oxide (IZO), (Tak, [0077], channel layer 55 comprises indium zinc oxide.)
Goda further discloses:
the second conductive layer (Goda, Fig. 2H, second channel material 119) is disposed over the first conductive layer. (Fig. 2H, second channel material 119 is disposed over the first conductive layer 118.)
Regarding claim 3, Tak and Goda disclose all the elements of claim 2.
Goda further discloses:
the second conductive layer comprises indium gallium zinc oxide (IGZO). (Goda, [0038], second channel material 119 is indium gallium zin oxide.)
Regarding 6, Tak and Goda disclose all the elements of claim 1.
Tak discloses the first conductive layer comprises a metal oxide that comprises indium (In). (Tak, [0077], the channel layer is made from indium zinc oxide.)
Goda discloses that the second conductive layer each comprises a metal oxide that comprises of indium (In). (Goda, [0038], the second channel material 119 is indium gallium zinc oxide.)
Regarding claim 7, Tak and Goda disclose all the elements of claim 6.
Tak further discloses wherein the first conductive layer comprises ZnSnO (Zinc Tin Oxide). (Tak, [0077], channel layer 54 is zinc tin oxide (ZnSnO).)
Goda further discloses the second conductive layer comprises InGaZnO. (Goda, [0038], the second channel material 119 is indium gallium zinc oxide.)
Regarding claim 8, Tak discloses:
A three-dimensional memory device, (Fig. 5A, semiconductor device) comprising:
a plurality of alternating layers formed over a surface of a substrate, (Fig. 5A, [0076], conductive layer 51 and insulating layer 52 are stacked in the vertical direction on a substrate.) wherein the alternating layers comprises a word line layer (conductive layer 51) and an inter-word line dielectric layer (insulating layer 52) that are stacked in a first direction;
a gate coupled to each of the word line layers of the plurality of alternating layers; ([0075], the conductive layers 51 may be gate electrodes.)
a multi-layer channel (annotated Fig. 5A, multi-layer channel) … extending in the first direction between the source region and the drain region, (the multi-layer channel extends in the vertical direction) wherein the multi-layer channel comprises:
a first conductive layer extending between the source region and the drain region; (Fig. 5A, channel region 54)
… and
a filler layer extending between the source region and the drain region; and (gap-fill insulating layer 55)
an intermediate layer (memory layer 53) stack disposed between the gates (conductive layer 51) and the multi-layer channel (annotated Fig. 5A, multi-layer channel), wherein the intermediate layer stack extends in the first direction between the source region and the drain region. (Fig. 5A, memory layer 53 extends in the vertical direction.)
While Tak does not directly discuss “a multi-layer channel (annotated Fig. 5A, multi-layer channel) having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region. The device of Tak would need to have a source and drain in order to be a functioning device.
However, Goda, which teaches an apparatus for 3D NAND flash memory devices (Goda, [0022]), discloses:
a multi-layer channel (Annotated Fig. 2H, multi-layer channel) having a first end coupled to a source region, ([0028], base conductive material is the source line.) a second end coupled to a drain region, ([0041], second plug material 124 being a drain contact) and extending in the first direction between the source region and the drain region, (Annotated Fig. 2H, multi-layer channel has a length in the vertical direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first end coupled to a source region, a second end coupled to a drain region, as taught by Goda in order to practice the invention of Tak.
Tak does not appear to disclose “a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer.”
Goda, which teaches an apparatus for 3D NAND flash memory devices (Goda, [0022]), discloses:
a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; and (Fig. 2H, second channel material 119. [0036], the second channel material is different than the first channel material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; as taught by Goda for purposes of improving reliability, lower leakage, and improve mobility. (Goda, [0039].)
Regarding claim 10, Tak and Goda disclose all the elements of claim 8.
Tak further discloses
wherein the first conductive layer comprises indium zinc oxide (IZO), (Tak, [0077], channel layer 55 comprises indium zinc oxide.)
Goda further discloses:
the second conductive layer (Goda, Fig. 2H, second channel material 119) is disposed over the first conductive layer. (Fig. 2H, second channel material 119 is disposed over the first conductive layer 118.)
Regarding claim 11, Tak and Goda disclose all the elements of claim 9.
Goda further discloses:
the second conductive layer comprises indium gallium zinc oxide (IGZO). (Goda, [0038], second channel material 119 is indium gallium zin oxide.)
Regarding claim 14, Tak and Goda disclose all the elements of claim 8.
Goda further discloses:
a material of the filler layer comprises silicon dioxide. ([0060], the central dielectric material 130 is silicon dioxide.)
Regarding claim 16, Tak and Goda disclose all the elements of claim 8.
Goda further discloses:
a material of the filler layer comprises silicon nitride. ([0060], the central dielectric material 130 is silicon nitride.)
Regarding claim 17, Tak and Goda disclose all the elements of claim 8.
Tak discloses the first conductive layer comprises a metal oxide that comprises indium (In). (Tak, [0077], the channel layer is made from indium zinc oxide.)
Goda discloses that the second conductive layer each comprises a metal oxide that comprises of indium (In). (Goda, [0038], the second channel material 119 is indium gallium zinc oxide.)
Regarding claim 18, Tak and Goda disclose all the elements of claim 8.
Tak further discloses wherein the first conductive layer comprises ZnSnO (Zinc Tin Oxide). (Tak, [0077], channel layer 54 is zinc tin oxide (ZnSnO).)
Goda further discloses the second conductive layer comprises InGaZnO. (Goda, [0038], the second channel material 119 is indium gallium zinc oxide.)
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Tak and Goda as applied to claim 8 under the first interpretation above, and further in view of Ino et al. US 20170077115 A1 (hereinafter Ino.)
Regarding claim 9, Tak and Goda discloses all the elements of claim 8 above, While Goda does disclose that wherein the intermediate layer stack comprises a nitride (Fig. 2H, nitride material 114.) Goda does not appear to disclose specifically that intermediate layer stack comprises at least one layer that comprises silicon nitride (SixNy) or hafnium oxide (HfOx).
Ino, which discloses a nonvolatile semiconductor memory device (Ino, Abstract), discloses:
the intermediate layer stack (Fig. 12, multi-film layer 123 includes a tunnel insulating layer 124, a charge accumulation layer 125, and a block insulating layer 126.) comprises at least one layer that comprises silicon nitride (SixNy) or hafnium oxide (HfOx). ([0054], charge accumulation layer 125 comprising of silicon nitride.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak and Goda to have the intermediate layer stack comprises at least one layer that comprises silicon nitride (SixNy) as taught by Ino for purposes of having an insulator capable of charge accumulation. (Ino, [0054].)
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tak and Goda as applied to claim 8 under the first interpretation above, and further in view of Zhang et al. US 20240421032 A1 (hereinafter Zhang).
Regarding claim 15, Tak and Goda disclose all the element of claim 8.
Neither Tak or Goda directly disclose that the filler layer comprises aluminum oxide. Tak discloses that the filler layer (Tak, Fig. 5A, gap-fill insulating layer 55.) is an insulating layer (Tak, [0055].) and Goda discloses that the filler layer (Goda, central dielectric material 130.) could be but is not limited to silicon dioxide or silicon nitride. (Goda, [0060].)
However, Zhang, which teaches a memory cell device (Zhang, Abstract), discloses a channel insulation layer 70 made of aluminum oxide. (Zhang, [0039].)
One of ordinary skill in the art before the effective filing date of the claimed invention to could have modified the device of Tak and Goda to have a filler layer that comprises of aluminum oxide as because substitution of silicon oxide or nitride insulative material from Tak or Goda for Zhang would have resulted the same device as recited by the claim with the same functionality.
Claims 1, 4, 5, 8, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Tak and Goda under this second interpretation.
This second interpretation of claim 1 will be used with regards to claims 4 and 5.
Regarding claim 1, Tak discloses:
A three-dimensional memory device, (Fig. 5A, semiconductor device) comprising:
a plurality of alternating layers formed over a surface of a substrate, (Fig. 5A, [0076], conductive layer 51 and insulating layer 52 are stacked in the vertical direction on a substrate.) wherein the alternating layers comprises a word line layer (conductive layer 51) and an inter-word line dielectric layer (insulating layer 52) that are stacked in a first direction;
a gate coupled to each of the word line layers of the plurality of alternating layers; ([0075], the conductive layers 51 may be gate electrodes.)
a multi-layer channel (annotated Fig. 5A, multi-layer channel) … extending in the first direction between the source region and the drain region, (the multi-layer channel extends in the vertical direction) wherein the multi-layer channel comprises:
…
a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; and (Fig. 5A, channel region 54)
an ONO layer stack (memory layer 53) disposed between the gate (conductive layer 51) and the multi-layer channel(annotated Fig. 5A, multi-layer channel), wherein the ONO layer stack extends in the first direction between the source region and the drain region. (Fig. 5A, memory layer 53 extends in the vertical direction.)
While Tak does not directly discuss “a multi-layer channel (annotated Fig. 5A, multi-layer channel) having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region”. The device of Tak would need to have a source and drain in order to be a functioning device.
However, Goda, which teaches an apparatus for 3D NAND flash memory devices (Goda, [0022]), discloses:
a multi-layer channel (Annotated Fig. 2H, multi-layer channel) having a first end coupled to a source region, ([0028], base conductive material is the source line.) a second end coupled to a drain region, ([0041], second plug material 124 being a drain contact) and extending in the first direction between the source region and the drain region, (Annotated Fig. 2H, multi-layer channel has a length in the vertical direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first end coupled to a source region, a second end coupled to a drain region, as taught by Goda in order to practice the invention of Tak.
Tak does not appear to disclose “a first conductive layer extending between the source region and the drain region.”
Goda further discloses:
a first conductive layer extending between the source region and the drain region; (Fig. 2H, second channel material 119. [0036], the second channel material is different than the first channel material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first conductive layer extending between the source region and the drain region as taught by Goda for purposes of improving reliability, lower leakage, and improve mobility. (Goda, [0039].)
Regarding claim 4, the second interpretation Tak and Goda disclose all the elements of claim 1.
Tak further discloses:
the second conductive layer comprises indium zinc oxide (IZO), (Tak, [0077], channel layer 55 comprises indium zinc oxide.) and
Goda further discloses:
the first conductive layer (second channel material 119) is disposed over the second conductive layer (first channel material 118). (Fig. 2H, second channel material 119 is disposed over the first conductive layer 118.)
Regarding claim 5, Tak and Goda disclose all the elements of claim 4.
Goda further discloses:
wherein the first conductive layer (Fig. 2H, second channel material 119) comprises indium gallium zinc oxide (IGZO). (Goda, [0038], first channel material 119 is indium gallium zin oxide.)
This second interpretation of claim 8 will be used with regards to claims 12 and 13.
Regarding claim 8, Tak discloses:
A three-dimensional memory device, (Fig. 5A, semiconductor device) comprising:
a plurality of alternating layers formed over a surface of a substrate, (Fig. 5A, [0076], conductive layer 51 and insulating layer 52 are stacked in the vertical direction on a substrate.) wherein the alternating layers comprises a word line layer (conductive layer 51) and an inter-word line dielectric layer (insulating layer 52) that are stacked in a first direction;
a gate coupled to each of the word line layers of the plurality of alternating layers; ([0075], the conductive layers 51 may be gate electrodes.)
a multi-layer channel (annotated Fig. 5A, multi-layer channel) … extending in the first direction between the source region and the drain region, (the multi-layer channel extends in the vertical direction) wherein the multi-layer channel comprises:
…
a second conductive layer extending between the source region and the drain region, wherein the first conductive layer is different from the second conductive layer; and (Fig. 5A, channel region 54)
a filler layer extending between the source region and the drain region; and (gap-fill insulating layer 55)
an intermediate layer (memory layer 53) stack disposed between the gates (conductive layer 51) and the multi-layer channel (annotated Fig. 5A, multi-layer channel), wherein the intermediate layer stack extends in the first direction between the source region and the drain region. (Fig. 5A, memory layer 53 extends in the vertical direction.)
While Tak does not directly discuss “a multi-layer channel (annotated Fig. 5A, multi-layer channel) having a first end coupled to a source region, a second end coupled to a drain region, and extending in the first direction between the source region and the drain region.” The device of Tak would need to have a source and drain in order to be a functioning device.
However, Goda, which teaches an apparatus for 3D NAND flash memory devices (Goda, [0022]), discloses:
a multi-layer channel (Annotated Fig. 2H, multi-layer channel) having a first end coupled to a source region, ([0028], base conductive material is the source line.) a second end coupled to a drain region, ([0041], second plug material 124 being a drain contact) and extending in the first direction between the source region and the drain region, (Annotated Fig. 2H, multi-layer channel has a length in the vertical direction.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first end coupled to a source region, a second end coupled to a drain region, as taught by Goda in order to practice the invention of Tak.
Tak does not appear to disclose “a first conductive layer extending between the source region and the drain region.”
Goda further discloses:
a first conductive layer extending between the source region and the drain region; (Fig. 2H, second channel material 119. [0036], the second channel material is different than the first channel material.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Tak to have a first conductive layer extending between the source region and the drain region as taught by Goda for purposes of improving reliability, lower leakage, and improve mobility. (Goda, [0039].)
Regarding claim 12, the second interpretation Tak and Goda disclose all the elements of claim 8.
Tak further discloses:
the second conductive layer comprises indium zinc oxide (IZO), (Tak, [0077], channel layer 55 comprises indium zinc oxide.) and
Goda further discloses:
the first conductive layer (second channel material 119) is disposed over the second conductive layer (first channel material 118). (Fig. 2H, second channel material 119 is disposed over the first conductive layer 118.)
Regarding claim 13, Tak and Goda disclose all the elements of claim 12.
Goda further discloses:
wherein the first conductive layer (Fig. 2H, second channel material 119) comprises indium gallium zinc oxide (IGZO). (Goda, [0038], first channel material 119 is indium gallium zin oxide.)
Conclusion
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812