DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II in the reply filed on 10/16/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 19, the recitation of “forming an inner spacer and within the space” in line 3 renders the claim as indefinite. It is unclear as to whether the intended recitation should have been “forming an inner spacer within the space” consistent with claim 15 or whether the phrase is missing a secondary limitation. With respect to claim 20, the recitation of “forming an inner spacer and within the space” in line 5 renders the claim as indefinite. It is unclear as to whether the intended recitation should have been “forming an inner spacer within the space” consistent with claim 14 or whether the phrase is missing a secondary limitation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 10-11, 13, and 16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (U.S. Publication No. 2023/0420367 A1; hereinafter Xie)
With respect to claim 10, Xie discloses a manufacturing method for a semiconductor device, comprising: forming a fin structure on the substrate [102], wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form a first active structure and a second active structure, wherein the trench extends in a second direction (See ¶[0055]-¶[0062]; Figure 2A-2D); forming a first insulation layer [108] within the first active structure; forming an epitaxy [126] within the trench; forming a first metal gate [124] within the first active structure, wherein the first insulation layer is formed under the first metal gate; and forming the back-side conductive via [144] to connect the epitaxy, wherein the first insulation layer extends to a first lateral surface of the back-side conductive via (see Figure 11A).
With respect to claim 11, Xie discloses forming a second metal gate [124] on the second active structure; and forming a second insulation layer [108] within the second active structure; wherein in forming the back-side conductive via to connect the epitaxy, the second insulation layer extends to a second lateral surface of the back-side conductive via (see Figure 11A).
With respect to claim 13, Xie discloses wherein the substrate has an upper surface on which the first active structure and the second active structure are formed, and in forming the first insulation layer within the first active structure, the first insulation layer is formed on the upper surface (See Figure 1A).
With respect to claim 16, Xie discloses wherein in forming the first insulation layer within the first active structure, the first insulation layer has a lateral surface; in forming the first metal gate within the first active structure, the first metal gate has a lateral surface, and the lateral surface of the first insulation layer is closer to the first lateral surface of the back-side conductive via than the lateral surface of the first metal gate (See Figure 11A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 12, 14-15, and 17-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Huang et al. (U.S Publication No. 2022/0028786 A1; hereinafter Huang)
With respect to claim 12, Xie fails to disclose further comprising: forming a pure silicon layer formed on a bottom of another trench; wherein in forming the back-side conductive via to connect the epitaxy, the first insulation layer extends between the pure silicon layer and the back-side conductive via in the first direction. In the same field of endeavor, Huang teaches forming a pure silicon layer [234] formed on a bottom of another trench; wherein in forming the back-side conductive via [262] to connect the epitaxy, the first insulation layer [256] extends between the pure silicon layer and the back-side conductive via in the first direction (See Figure 20). Implementation of pure silicon within the trench structures of Xie as taught by Huang facilitates the epitaxy growth within the trench structure (see Huang ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 14, Xie discloses wherein forming the trench passing through the fin structure to form the first active structure and the second active structure, the first active structure comprises a plurality of sheets (See ¶[0057]), but fails to disclose the manufacturing method further comprise: forming a high-k dielectric layer covering the sheets, wherein the high-k dielectric layer and the first insulation layer are formed of the same material. In the same field of endeavor, Huang teaches forming a high-k dielectric layer [226] covering the sheets, wherein the high-k dielectric layer and the first insulation layer [256] are formed of the same material (See ¶[0024] and ¶[0034]). Implementation of the high-k dielectric material for insulation as taught by Huang facilitates proper isolation of the gate structures and fin structures of Xie (See Huang ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 15, Xie discloses wherein forming the trench passing through the fin structure to form the first active structure and the second active structure, the first active structure comprises a plurality of sheets and a space, the space is formed between adjacent two of the sheets (See ¶[0057], ¶[0059], and ¶[0064]); in forming the first metal gate within the first active structure, a portion of the metal gate is formed within the space (See Figure 4A); but fails to disclose the manufacturing method further comprises: forming an inner spacer within the space, wherein the inner spacer and the first insulation layer are formed of the same material.
In the same field of endeavor, Huang teaches forming an inner spacer [226] within the space, wherein the inner spacer and the first insulation layer [256] are formed of the same material (See ¶[0024] and ¶[0034]). Implementation of the inner spacer material consistent with the first insulation layer as taught by Huang facilitates proper isolation of the gate structures and fin structures of Xie (See Huang ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 17, Xie discloses forming an oxide layer [104] over the substrate; but fails to disclose forming a cushion layer over oxide layer, wherein the cushion layer is lower than the first metal gate and higher than the first insulation layer. Huang teaches forming a cushion layer [206] over substrate and oxide layer [256], wherein the cushion layer is lower than the first metal gate and higher than the first insulation layer (see Figure 21B). The cushion layer of Huang allows for substantial enough spacing to provide good isolation between the backside contact and the semiconductor layer while minimizing resistance within the device (See Huang ¶[0016]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 18, Xie discloses a manufacturing method for a semiconductor device, comprising: forming a fin structure on the substrate [102], wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form an active structure, wherein the trench extends in a second direction (See ¶[0055]-¶[0062]; Figures 2A-2D), the active structure comprises a plurality of sheets [112] and a spacer [110] (See ¶[0057], ¶[0059], and ¶[0064]), the spacer is formed between adjacent two of the sheets, and each spacer is formed of silicon-germanium (See ¶[0057]); forming a hard mask within a bottom of the trench to cover a lateral surface of the lowermost spacer [108]; removing the spacer which is not covered by the hard mask to form a plurality of spaces, wherein the lowermost spacer is retained (see ¶[0064]); removing the hard mask to expose the lowermost spacer; forming an oxide spacer [114/118] within the space (See ¶[0051] and Figure 4A). Xie fails to disclose removing the lowermost spacer to form a lowermost space; and forming the insulation layer within the lowermost space, however Xie discloses insulating layer [108] in its final orientation. In the same field of endeavor, Huang teaches removing the lowermost spacer to form a lowermost space; and forming the insulation layer within the lowermost space (See Figure 15-16; ¶[0034]). Implementation of a selective removal process to produce the insulating layer as taught by Huang allows for thickness control of the insulating layer to provide proper isolation from the backside via (See Huang ¶[0036]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 19, the combination of Xie and Huang discloses wherein forming the insulation layer within the lowermost space further comprises: forming an inner spacer [226] and within the space, wherein the inner spacer and the insulation layer [256] are formed of the same material (See Huang ¶[0024] and ¶[0034]).
With respect to claim 20, the combination of Xie and Huang discloses wherein in forming the insulation layer within the lowermost space, the insulation layer is formed of a high-k dielectric material; after forming the insulation layer within the lowermost space, the manufacturing method further comprises: forming an inner spacer [226] and within the space (See Huang ¶[0024] and ¶[0034]).
With respect to claim 21, Xie discloses a manufacturing method for a semiconductor device, comprising: forming a fin structure on the substrate [102], wherein the fin structure extends in a first direction; forming a trench passing through the fin structure to form a first active structure and a second active structure, wherein the trench extends in a second direction (See ¶[0055]-¶[0062]; Figure 2A-2D); forming a first insulation layer [108] within the first active structure; forming an epitaxy [126] within the trench; forming a first metal gate [124] within the first active structure, wherein the first insulation layer is formed under the first metal gate; forming a second insulation layer [108] within the second active structure; and forming the back-side conductive via [144] to connect the epitaxy, wherein the first insulation layer extends to a first lateral surface of the back-side conductive via (See Figure 4A). Xie fails to disclose the back-side conductive via has a width greater than an interval between the first insulation layer and the second insulation layer.
In the same field of endeavor, Huang teaches the back-side conductive via [262/270] has a width greater than an interval between the first insulation layer and the second insulation layer (see Figure 19-20). Implementation of a backside via with expanded with as taught by Huang allows for increased surface area for contact with exterior structures (see Figure 21B and ¶[0038]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 22, the combination of Xie and Huang discloses forming a second metal gate [124] on the second active structure; and wherein in forming the back-side conductive via to connect the epitaxy, the second insulation layer extends to a second lateral surface of the back-side conductive via (See Xie Figure 11A).
With respect to claim 23, the combination of Xie and Huang discloses forming a pure silicon layer [234] formed on a bottom of another trench; wherein in forming the back-side conductive via to connect the epitaxy, the first insulation layer [256] extends between the pure silicon layer and the back-side conductive via in the first direction (See Figure 20). Implementation of pure silicon within the trench structures of Xie as taught by Huang facilitates the epitaxy growth within the trench structure (see Huang ¶[0027]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 24, the combination of Xie and Huang discloses wherein the substrate has an upper surface on which the first active structure and the second active structure are formed, and in forming the first insulation layer within the first active structure, the first insulation layer is formed on the upper surface (See Xie Figure 1A).
With respect to claim 25, the combination of Xie and Huang discloses wherein forming the trench passing through the fin structure to form the first active structure and the second active structure, the first active structure comprises a plurality of sheets (See Xie ¶[0057]); the manufacturing method further comprise: forming a high-k dielectric layer covering the sheets, wherein the high-k dielectric layer and the first insulation layer are formed of the same material (See Huang [226]; ¶[0024] and ¶[0034]). Implementation of the high-k dielectric material for insulation as taught by Huang facilitates proper isolation of the gate structures and fin structures of Xie (See Huang ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 26, the combination of Xie and Huang discloses wherein forming the trench passing through the fin structure to form the first active structure and the second active structure, the first active structure comprises a plurality of sheets and a space, the space is formed between adjacent two of the sheets (See ¶[0057], ¶[0059], and ¶[0064]); in forming the first metal gate within the first active structure, a portion of the metal gate is formed within the space (See Figure 4A); the manufacturing method further comprises: forming an inner spacer within the space, wherein the inner spacer and the first insulation layer are formed of the same material (See Huang ¶[0024] and ¶[0034]). Implementation of the inner spacer material consistent with the first insulation layer as taught by Huang facilitates proper isolation of the gate structures and fin structures of Xie (See Huang ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 27, the combination of Xie and Huang discloses wherein in forming the first insulation layer within the first active structure, the first insulation layer has a lateral surface; in forming the first metal gate within the first active structure, the first metal gate has a lateral surface, and the lateral surface of the first insulation layer is closer to the first lateral surface of the back-side conductive via than the lateral surface of the first metal gate (See Xie Figure 11A).
With respect to claim 28, the combination of Xie and Huang discloses forming an oxide layer [104] over the substrate (See Xie Figure 4A; and forming a cushion layer [206] over oxide layer, wherein the cushion layer is lower than the first metal gate and higher than the first insulation layer (see Huang Figure 21B). The cushion layer of Huang allows for substantial enough spacing to provide good isolation between the backside contact and the semiconductor layer while minimizing resistance within the device (See Huang ¶[0016]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
With respect to claim 29, the combination of Xie and Huang discloses wherein the first active structure comprises a plurality of sheets and a space, the space is formed between adjacent two of the sheets, and the space has a first width; in forming the first insulation layer within the first active structure, the first insulation layer has a second width substantially equal to the first width (see Xie Figure 2A).
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818