DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8 and 14 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Martorell et al. (Martorell) (US 2021/0111113 A1) in view of Chang et al. (Chang) (US 2022/0302078 A1) in view of Qui (CN 115376938 A1).
In regards to claim 1, Martorell (Figs. 1-6 and associated text) discloses a method for forming a multiple die stack (2A-3B), comprising: forming a first circuit wafer (item 110) with multiple first circuit dies (items 120A-D), each first circuit die (item 120A-D) has a power and circuit layer (shown but not labeled in Figs. 3A, 3B) underlying a power and signal layer (shown but not labeled in Figs. 3A, 3B); forming an interposer wafer (item 150), each interposer die (items 170A-170I) has a power and signal layer (shown but not labeled in Figs. 3A, 3B) underlying a power via and signal via layer (shown but not labeled in Figs. 3A, 3B); and hybrid bonding a top surface of the first circuit die (item 120A-D) to a bottom surface of the interposer wafer (item 150) to form a first bonded structure (Figs. 3A, 3B) with electrical power and signal connections between the multiple first circuit dies (item 120A-D) and the multiple interposer dies (item 1170), wherein the interposer wafer (item 150) provides structural support of the first bonded structure (Figs. 3A, 3B) during subsequent processing, but does not specifically disclose wafer-to-wafer (hybrid) bonding or a first bonded wafer.
Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) discloses device wafer (item 50) with multiple device dies (item 50) and hybrid bonding (paragraph 47, wafer-to-wafer bonding).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chang for the purpose of device density and forming multiple packages if so desired.
Martorell (Figs. 1-6 and associated text) as modified Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) discloses hybrid bonding a top surface of the first circuit wafer (item 110, Martorell, wafer-to-wafer bonding, Chang) to a bottom surface of the interposer wafer (item 150, Martorell, wafer-to-wafer bonding, Chang) to form a first bonded wafer (items 110 plus 150, Martorell).
Martorell as modified by Chang does not specifically disclose a first circuit support layer on a bottom of the first circuit wafer and an interposer support layer on the top of the interposer wafer.
QIU (Figs. 1E-1S and associated text) discloses a first circuit support layer (item 124) on a bottom of the first circuit wafer (item 10a), and an interposer support layer (item 124) on a top of the interposer wafer (item 10b). Examiner notes that the Applicant has not given a special definition to the term on, therefor certain features can be “directly” or “indirectly” on certain claimed features.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Qui for the purpose of support/protection during processing.
In regards to claim 2, QIU (Figs. 1E-1S and associated text) discloses flipping the first bonded wafer (items 10a plus 10b) to expose the first circuit support layer (item 124) of the first circuit wafer (item 10a); and performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer (item 10a) to remove the first circuit support layer (item 14) to expose a plurality of power vias in the power and circuit layer of the first circuit wafer (item 10a).
Claim(s) 3-8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Martorell et al. (Martorell) (US 2021/0111113 A1) in view of Chang et al. (Chang) (US 2022/0302078 A1) in view of QIU (CN 115376938 A) as applied to claims 1 and 2 above and further in view of Lee et al. (Lee) (US 2022/0165721 A1 now US 11,862,618 B2)
In regards to claim 3, Martorell as modified by Chang Qui does not specifically disclose forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts, wherein the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer.
Lee (Figs. 9, 19-22 and associated text) discloses forming a power delivery network (PDN) layer (item PDN) directly on the first circuit wafer, the PDN layer (item PDN) having a top surface with internal power contacts interfacing with the power and circuit layer (item 10) of the first circuit wafer (items 10 plus IC) and a bottom surface with external power contacts (item 50, Fig. 9), wherein the internal power contacts of the PDN layer (item PDN) make contact with the power and circuit layer (item 10) to electrically connect the internal power contacts of the PDN layer (item PDN) to the plurality of power vias in the power and circuit layer (item 10) of the first circuit wafer (items 10 plus IC) to form a second bonded wafer (items PDC plus IC plus 10 plus PDN) from the first bonded wafer (items PDC plus IC plus 10).
Therefore it would have been obvious to one of ordinary skill in art before the effective filing date to incorporate the teachings of Lee for the purpose of power distribution.
In regards to claim 4, Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text), QIU (Figs. 1E-1S and associated text) and Lee (Figs. 9, 19-22 and associated text) discloses flipping the second bonded wafer (items 10a plus 10b, QI plus item PDN, Lee) to expose the top surface of the interposer wafer (item 10b); and performing a second CMP process or a second etching process on the interposer support layer (item 124) to expose contact points of the power via and signal via layer (item 22) of the interposer wafer (item 10b).
In regards to claim 5, Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text), QIU (Figs. 1E-1S and associated text) and Lee (Figs. 9, 19-22 and associated text) does not specifically disclose reducing the interposer wafer (item 10b) to a total thickness of approximately 100 microns to approximately 200 microns when using vias with a critical dimension of approximately 5 microns to approximately 20 microns.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a reduces thickness of approximately 100 to 200 microns, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 6, , Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) and QIU (Figs. 1E-1S and associated text) discloses reducing the interposer wafer to a total thickness of approximately 5 microns to approximately 10 microns (12 mm) when using vias with a critical dimension of approximately 2 microns to approximately 4 microns.
In regards to claim 7, Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) and QIU (Figs. 1E-1S and associated text) discloses forming a second circuit wafer (item 110, Martorell, Chang 50, items 10”, QUI) with multiple second circuit dies (item 110, Martorell, Chang 50, items 10”, QUI), each second circuit die (item 110, Martorell, Chang 50, items 10”, QUI) having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies (item 110, Martorell, Chang 50, items 10” or 10b, QUI) of the interposer wafer (item 110, Martorell, Chang 50, items 10b, QUI).
It would have been obvious to modify the invention to include a second circuit wafer for the purpose of device density, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
In regards to claim 8, Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) and QIU (Figs. 1E-1S and associated text) and Lee (Figs. 9, 19-22 and associated text) discloses hybrid bonding the bottom surface of the second circuit wafer (Chang 50, items 10”, QUI) to the top surface of the interposer wafer (Chang 50, items 10b, QUI) to form a third bonded wafer (items 10” plus 10a plus 10b, QUI plus item PDN, Lee) from the second bonded wafer (items 10a plus 10b, QII plus item PDN) to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer; and dicing the third bonded wafer (items 10” plus 10a plus 10b, QUI plus item PDN, Lee) to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer (item PDN, Lee), one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability.
In regards to claim 14, Martorell (Figs. 1-6 and associated text) discloses a method for forming a multiple die stack (2A-3B), comprising: forming a first circuit wafer (item 110) with multiple first circuit dies (items 120A-D), each first circuit die (item 120A-D) has a power and circuit layer (shown but not labeled in Figs. 3A, 3B) underlying a power and signal layer (shown but not labeled in Figs. 3A, 3B); forming an interposer wafer (item 150), each interposer die (items 170A-170I) has a power and signal layer (shown but not labeled in Figs. 3A, 3B) underlying a power via and signal via layer (shown but not labeled in Figs. 3A, 3B); and hybrid bonding a top surface of the first circuit die (item 120A-D) to a bottom surface of the interposer wafer (item 150) to form a first bonded structure (Figs. 3A, 3B) with electrical power and signal connections between the multiple first circuit dies (item 120A-D) and the multiple interposer dies (item 1170), wherein the interposer wafer (item 150) provides structural support of the first bonded structure (Figs. 3A, 3B) during subsequent processing, but does not specifically disclose wafer-to-wafer (hybrid) bonding or a first bonded wafer.
Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) discloses device wafer (item 50) with multiple device dies (item 50) and hybrid bonding (paragraph 47, wafer-to-wafer bonding).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Chang for the purpose of device density and forming multiple packages if so desired.
Martorell (Figs. 1-6 and associated text) as modified Chang (paragraphs 17, 18, 47, Fig. 1 and associated text) discloses hybrid bonding a top surface of the first circuit wafer (item 110, Martorell, wafer-to-wafer bonding, Chang) to a bottom surface of the interposer wafer (item 150, Martorell, wafer-to-wafer bonding, Chang) to form a first bonded wafer (items 110 plus 150, Martorell).
Martorell as modified by Chang does not specifically disclose a first circuit support layer on a bottom of the first circuit wafer and an interposer support layer on the top of the interposer wafer.
QIU (Figs. 1E-1S and associated text) discloses a first circuit support layer (item 124) on a bottom of the first circuit wafer (item 10a), and an interposer support layer (item 124) on a top of the interposer wafer (item 10b). Examiner notes that the Applicant has not given a special definition to the term on, therefor certain features can be “directly” or “indirectly” on certain claimed features.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Qui for the purpose of support/protection during processing.
Martorell as modified by Chang Qui does not specifically disclose forming a power delivery network (PDN) layer directly on the first circuit wafer, the PDN layer having a top surface with internal power contacts interfacing with the power and circuit layer of the first circuit wafer and a bottom surface with external power contacts, wherein the internal power contacts of the PDN layer make contact with the power and circuit layer to electrically connect the internal power contacts of the PDN layer to the plurality of power vias in the power and circuit layer of the first circuit wafer to form a second bonded wafer from the first bonded wafer.
Lee (Figs. 9, 19-22 and associated text) discloses forming a power delivery network (PDN) layer (item PDN) directly on the first circuit wafer, the PDN layer (item PDN) having a top surface with internal power contacts interfacing with the power and circuit layer (item 10) of the first circuit wafer (items 10 plus IC) and a bottom surface with external power contacts (item 50, Fig. 9), wherein the internal power contacts of the PDN layer (item PDN) make contact with the power and circuit layer (item 10) to electrically connect the internal power contacts of the PDN layer (item PDN) to the plurality of power vias in the power and circuit layer (item 10) of the first circuit wafer (items 10 plus IC) to form a second bonded wafer (items PDC plus IC plus 10 plus PDN) from the first bonded wafer (items PDC plus IC plus 10).
Therefore it would have been obvious to one of ordinary skill in art before the effective filing date to incorporate the teachings of Lee for the purpose of power distribution.
Martorell (Figs. 1-6 and associated text) as modified by as modified by Chang (paragraphs 17, 18, 47, Fig. 1 and associated text), QIU (Figs. 1E-1S and associated text) and Lee (Figs. 9, 19-22 and associated text) discloses flipping the second bonded wafer (items 10a plus 10b, QI plus item PDN, Lee) to expose the top surface of the interposer wafer (item 10b); and performing a second CMP process or a second etching process on the interposer support layer (item 124) to expose contact points of the power via and signal via layer (item 22) of the interposer wafer (item 10b); forming a second circuit wafer (item 110, Martorell, Chang 50, items 10”, QUI) with multiple second circuit dies (item 110, Martorell, Chang 50, items 10”, QUI), each second circuit die (item 110, Martorell, Chang 50, items 10”, QUI) having a bottom surface with at least one signal contact and at least one power contact for electrically interconnecting with the multiple interposer dies (item 110, Martorell, Chang 50, items 10” or 10b, QUI) of the interposer wafer (item 110, Martorell, Chang 50, items 10b, QUI); hybrid bonding the bottom surface of the second circuit wafer (Chang 50, items 10”, QUI) to the top surface of the interposer wafer (Chang 50, items 10b, QUI) to form a third bonded wafer (items 10” plus 10a plus 10b, QUI plus item PDN, Lee) from the second bonded wafer (items 10a plus 10b, QII plus item PDN) to electrically connect the at least one signal contact and the at least one power contact to the multiple interposer dies of the interposer wafer; and dicing the third bonded wafer (items 10” plus 10a plus 10b, QUI plus item PDN, Lee) to form electrically connected vertical die stacks, each vertical die stack has one portion of the PDN layer (item PDN, Lee), one of the first circuit die, one of the interposer die, and one of the second circuit die to form a complete vertical die stack with backside power capability, but does not specifically disclose that a thickness of the interposer wafer is approximately 100 microns to 200 microns.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a thickness of the interposer wafer being approximately 100 microns to 200 microns, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 June 8, 2026
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