Prosecution Insights
Last updated: August 17, 2026
Application No. 18/200,683

PHOTODETECTORS WITH ONE OR MORE CONFINING FEATURES

Non-Final OA §103
Filed
May 23, 2023
Examiner
DEGRASSE, IAN ISAAC
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Globalfoundries U S Inc.
OA Round
3 (Non-Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
19 granted / 24 resolved
+11.2% vs TC avg
Minimal +1% lift
Without
With
+1.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
49 currently pending
Career history
76
Total Applications
across all art units

Statute-Specific Performance

§103
54.3%
+14.3% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
12.5%
-27.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 24 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 15, 2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 3, 6-7, 11-12, 16-17 and 19-27 are rejected under 35 U.S.C. 103 as being obvious over US 2022/0115546 A1 to Aboketaf et al. (hereinafter “Aboketaf” – previously cited reference) in view of US 2022/0107461 A1 to Dosunmu et al. (hereinafter “Dosunmu” – newly cited reference). Regarding claim 1, Aboketaf discloses a structure for a photonics chip, the structure comprising: a first dielectric layer (photonics chip structure 10 having dielectric layer 14; Fig. 2; paragraph [0025]); a photodetector including a pad disposed on the first dielectric layer and a semiconductor layer on the pad, the semiconductor layer having a first sidewall (photonics chip structure 10 having a photodetector including a photodetector pad 20 on layer 14 and having portions of germanium light-absorbing layer 34 disposed thereon, where layer 34 has first sidewall; Figs. 6-6A; paragraphs [0001], [0025]-[0026], [0032]), the pad comprising a semiconductor material, the pad including a top surface, a first doped region adjacent to the first sidewall of the semiconductor layer, a first trench in the first doped region that extends from the top surface partially through the pad toward the first dielectric layer, a first side edge, and a second side edge (pad 20 having semiconductor material, top surface, first part of doped region 48, 50 adjacent first sidewall, trench disposed within region 48, 50 from top surface towards layer 14, and first and second side edges; Figs. 6-6A and 7-7A; paragraphs [0025]-[0026], [0030]); a waveguide core disposed on the first dielectric layer, the waveguide core including a tapered section adjacent to the first side edge of the pad (waveguide core 18 disposed over layer 14 and having tapered section adjacent side edge of pad 20; Figs. 5-6A; paragraph [0027]); and a first confining feature adjacent the first trench of the pad, the first confining feature positioned laterally between the second side edge of the pad and the first sidewall of the semiconductor layer, and the first confining feature comprising a dielectric material (first dielectric STI regions 24 disposed adjacent trench of pad 20 and laterally between second side edge of pad 20 and first sidewall of layer 34; Figs. 5-6A; paragraph [0026]). Aboketaf fails to disclose a first confining feature inside the first trench of the pad. However, Dosunmu discloses a first confining feature inside the first trench of the pad, the first confining feature positioned laterally between the second side edge of the pad and the first sidewall of the semiconductor layer, and the first confining feature comprising a dielectric material (portion of dielectric layer 114 inside trench of SOI 104 and disposed laterally between side edge of SOI 104 and sidewall of Ge PD 108; Fig. 1B; paragraphs [0015]-[0017]). Aboketaf and Dosunmu are both considered to be analogous to the claimed invention because they are in the same field of germanium-based waveguide photodetectors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Dosunmu in order to potentially provide a stronger optical mode confinement within the Ge absorber given that a dielectric material placed inside the trench creates a higher index contrast boundary in immediate proximity to the absorbing volume. Further, such modification potentially provides reduced effective device capacitance and improved high-speed performance while providing better electrical isolation by limiting surface leakage paths. Regarding claim 3, Aboketaf in view of Dosunmu discloses structure of claim 1. Aboketaf further discloses wherein the first trench has a uniform depth relative to the top surface (first dielectric STI region 24 disposed in trenches; Figs. 5-6A; paragraph [0026]). Regarding claim 6, Aboketaf in view of Dosunmu discloses the structure of claim 25. Aboketaf further discloses wherein the first trench and the second trench extend to equal depths in the pad (first region 24 in a first trench in pad 20 and layer 34 disposed in a second trench in pad 20, where the first trench extends to the same depth as the second trench and beyond; Figs. 6-6A). Regarding claim 7, Aboketaf in view of Dosunmu discloses the structure of claim 25. Aboketaf further discloses wherein the first trench and the second trench extend to unequal depths in the pad (first region 24 in a first trench in pad 20 and layer 34 disposed in a second trench in pad 20, where the first trench extends to the same depth as the second trench and beyond; Figs. 6-6A). Regarding claim 11, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the pad includes a second side edge opposite from the first side edge, and the first confining feature extends from the first side edge to the second side edge (pad 20 comprises second edge opposite the first edge where first region 24 extends horizontally from first to second edge; Fig. 5). Regarding claim 12, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the first trench in the pad has a length that is oriented parallel to the first sidewall of the semiconductor layer (pad 20 has trench containing first region 24 with length parallel to first sidewall of layer 34; Figs. 6-6A). Regarding claim 16, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses further comprising: a second dielectric layer that overlaps with the first confining feature (dielectric layer 26 overlapping with STI region 24; Fig. 4A; paragraph [0028]). Regarding claim 17, Aboketaf in view of Dosunmu discloses the structure of claim 16. Aboketaf further discloses further comprising: a third dielectric layer on the second dielectric layer; a doped region in the pad; and a contact extending through the second dielectric layer and the third dielectric layer to the doped region (middle-of-line (MOL) processing and back-end-of-line (BEOL) processing may be performed, which includes formation of silicide, contacts, vias, and wiring for an interconnect structure that is coupled with the photodetectors, in particular, separate sets of contacts may be formed in dielectric layers that respectively extend to the doped regions 48, 50; paragraph [0042]). Regarding claim 19, Aboketaf in view of Dosunmu discloses the structure of claim 16. Aboketaf further discloses wherein the dielectric material of the first confining feature is silicon dioxide, and the second dielectric layer comprises silicon nitride (STI region 24 comprising silicon dioxide and dielectric layer 26 comprising silicon nitride; paragraphs [0026], [0028]). Regarding claim 20, Aboketaf discloses a method of forming a structure for a photonics chip, the method comprising: forming a photodetector that includes a pad disposed on a dielectric layer, wherein the pad comprises a semiconductor material (photonics chip structure 10 having a photodetector including a photodetector pad 20 on layer 14, where pad 20 has portions of germanium light-absorbing layer 34; paragraphs [0001], [0025]-[0026], [0032]); forming a semiconductor layer of the photodetector that is positioned on the pad (pad 20 having portions of germanium light-absorbing layer 34 disposed thereon; Figs. 6-6A; paragraphs [0001], [0025]-[0026], [0032]); forming a doped region of the photodetector in the pad adjacent to a sidewall of the semiconductor layer (doped region 48, 50 formed in photodetector pad 20 adjacent sidewalls of layer 34; Figs. 7-7A); forming a trench in the doped region that extends from a top surface of the pad partially through the pad toward the dielectric layer (trench disposed within doped region 48, 50 and extending from top surface of pad 20 towards layer 14; Figs. 6-6A; paragraphs [0025]-[0026], [0030]); forming a waveguide core disposed on the dielectric layer, wherein the waveguide core includes a tapered section adjacent to a first side edge of the pad (waveguide core 18 disposed over layer 14 and having tapered section adjacent side edge of pad 20; Figs. 5-6A; paragraph [0027]); and forming a confining feature adjacent the trench of the pad, wherein the confining feature is positioned laterally between a second side edge of the pad and the sidewall of the semiconductor layer, and the confining feature comprises a dielectric material (first dielectric STI regions 24 disposed adjacent trench of pad 20 and laterally between second side edge of pad 20 and first sidewall of layer 34; Figs. 5-6A; paragraph [0026]). Aboketaf fails to disclose forming a confining feature inside the trench of the pad. However, Dosunmu discloses forming a confining feature inside the trench of the pad, wherein the confining feature is positioned laterally between a second side edge of the pad and the sidewall of the semiconductor layer, and the confining feature comprises a dielectric material (portion of dielectric layer 114 inside trench of SOI 104 and disposed laterally between side edge of SOI 104 and sidewall of Ge PD 108; Fig. 1B; paragraphs [0015]-[0017]). Aboketaf and Dosunmu are both considered to be analogous to the claimed invention because they are in the same field of germanium-based waveguide photodetectors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Dosunmu in order to potentially provide a stronger optical mode confinement within the Ge absorber given that a dielectric material placed inside the trench creates a higher index contrast boundary in immediate proximity to the absorbing volume. Further, such modification potentially provides reduced effective device capacitance and improved high-speed performance while providing better electrical isolation by limiting surface leakage paths. Regarding claim 21, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the first confining feature and the first trench are laterally positioned between the second side edge of the pad and the first sidewall of the semiconductor layer (pad 20 having second side edge with STI region 24 and trench disposed between the second side edge and first sidewall of layer 34; Figs. 6-6A). Regarding claim 22, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the first doped region is positioned between the second side edge of the pad and the first sidewall of the semiconductor layer (doped region 48, 50 of pad 20 disposed between second side edge of pad 20 and first sidewall of layer 34; Figs. 6-6A). Regarding claim 23, Aboketaf in view of Dosunmu discloses the structure of claim 22. Aboketaf further discloses wherein the first doped region includes a first portion between the second side edge of the pad and the first confining feature (first portion of doped region 48, 50 between second side edge of pad and STI region 24; Figs. 5-6A), the first doped region includes a second portion between the first sidewall of the semiconductor layer and the first confining feature (second portion of doped region 48, 50 between first sidewall of layer 34 and STI region 24; Figs. 5-6A), and the first doped region includes a third portion beneath the first confining feature and the first dielectric layer (doped region 48, 50 includes third portion disposed beneath a portion of STI region 24 and to dielectric layer 14; Figs. 7-7A). Regarding claim 24, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the pad includes a second trench that extends from the top surface partially through the pad toward the first dielectric layer, and the semiconductor layer is positioned inside the second trench of the pad (pad 20 includes second trench extending from top surface thereof toward layer 14 with layer 34 inside trench; Figs. 5-6A). Regarding claim 25, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf further discloses wherein the semiconductor layer has a second sidewall opposite from the first sidewall, the pad includes a second doped region adjacent to the second sidewall of the semiconductor layer (second part of doped region 48, 50 adjacent second sidewall of layer 34 opposite first sidewall; Figs. 7-7A), a second trench in the second doped region that extends from the top surface partially through the pad toward the first dielectric layer (pad 20 includes second trench in region of second part of doped region 48, 50 extending from top surface thereof toward layer 14; Figs. 5-6A), and a third side edge opposite from the second side edge (third side edge of pad 20 opposite from second edge; Figs. 5-6A). Regarding claim 26, Aboketaf in view of Dosunmu discloses the structure of claim 25. Aboketaf further discloses further comprising: a second confining feature adjacent the second trench of the pad (STI region 24 adjacent second trench of pad 20; Figs. 5-6A), the second confining feature laterally between the third side edge of the pad and the second sidewall of the semiconductor layer, and the second confining feature comprising the dielectric material (dielectric STI region 24 disposed laterally between third side edge of pad 20 and second sidewall of layer 24; Figs. 5-6A). Aboketaf fails to disclose a second confining feature inside the second trench of the pad. However, Dosunmu discloses a second confining feature inside the second trench of the pad (second portion of dielectric layer 114 inside second trench of SOI 104 and disposed laterally between side edge of SOI 104 and sidewall of Ge PD 108; Fig. 1B; paragraphs [0015]-[0017]). Aboketaf and Dosunmu are both considered to be analogous to the claimed invention because they are in the same field of germanium-based waveguide photodetectors. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Dosunmu in order to potentially provide a stronger optical mode confinement within the Ge absorber given that a dielectric material placed inside the trench creates a higher index contrast boundary in immediate proximity to the absorbing volume. Further, such modification potentially provides reduced effective device capacitance and improved high-speed performance while providing better electrical isolation by limiting surface leakage paths. Regarding claim 27, Aboketaf in view of Dosunmu discloses the structure of claim 26. Aboketaf further discloses wherein the first doped region is positioned between the second side edge of the pad and the first sidewall of the semiconductor layer (first part of doped region 48, 50 disposed between second side edge of pad 20 and first sidewall of layer 34; Figs. 5-7A), and the second doped region is positioned between the third side edge of the pad and the second sidewall of the semiconductor layer (second part of doped region 48, 50 disposed between third side edge of pad 20 and second sidewall of layer 34; Figs. 5-7A). Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf in further view of Dosunmu and US 10,241,269 B1 to Jacob et al. (hereinafter “Jacob” – previously cited reference). Regarding claim 4, Aboketaf in view of Dosunmu discloses the structure of claim 1 wherein the first trench has a first portion and a second portion, the first portion of the first trench is disposed adjacent to the first sidewall (first dielectric STI regions 24 disposed in trench into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]). Aboketaf fails to disclose the first portion of the first trench has a shallower depth relative to the top surface than the second portion of the first trench. However, Jacob discloses the first portion of the first trench has a shallower depth relative to the top surface than the second portion of the first trench (trench filled with dielectric material 22 and having first and second portions where first portion of trench is shallower to top surface of semiconductor structure 10a relative second portion of trench; abstract; Fig. 1; column 3, lines 11-53). Aboketaf and Jacob are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Jacob in order to potentially provide compact polarization mode conversion, enhanced mode confinement and reduced crosstalk, and minimization of higher-order mode excitation and absorption losses. Regarding claim 5, Aboketaf in view of Dosunmu discloses the structure of claim 1 wherein the first trench has a first portion and a second portion, the first portion of the first trench is disposed adjacent to the first sidewall (first dielectric STI regions 24 disposed in trench into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]). Aboketaf fails to disclose the second portion of the first trench has a shallower depth relative to the top surface than the first portion of the first trench. However, Jacob discloses the second portion of the first trench has a shallower depth relative to the top surface than the first portion of the first trench (trench filled with dielectric material 22 and having first and second portions where second portion of trench is shallower to top surface of semiconductor structure 10a relative first portion of trench; abstract; Fig. 1; column 3, lines 11-53). Aboketaf and Jacob are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Jacob in order to potentially provide compact polarization mode conversion, enhanced mode confinement and reduced crosstalk, and minimization of higher-order mode excitation and absorption losses. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf in view of Dosunmu and US 2021/0191042 A1 to Peng et al. (hereinafter “Peng” – previously cited reference). Regarding claim 14, Aboketaf in view of Dosunmu discloses the structure of claim 1. Aboketaf fails to disclose wherein the first confining feature comprises a plurality of segments arranged in a metamaterial structure. However, Peng discloses wherein the first confining feature comprises a plurality of segments arranged in a metamaterial structure (metamaterial structures 116 disposed in alternating layers with insulating layers 118 therebetween in a horizontal stack; Fig. 1A; paragraphs [0028], [0033]-[0036]). Aboketaf and Peng are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Peng in order to potentially provide improved mode confinement and reduced crosstalk, enhanced integration density, and low propagation loss and broadband operation. Response to Arguments Applicant’s arguments submitted June 15, 2026 have been fully considered. Specifically, Applicant substantively amended the independent claims and submitted new claims 23-27 with corresponding arguments that these amendments overcome the previous rejection. Examiner agrees that the amended independent claims overcome the previous 35 USC 103 rejection using Aboketaf. However, a new ground of rejection of these claims necessitated by the amendments is presented using Aboketaf in view of Dosunmu. Further, regarding claim 16, Applicant asserts that the dielectric layer 26 cannot be used to disclose this claim limitation because layer 26 “may be removed” in subsequent steps according to paragraph [0031]. Applicant takes this to mean layer 26 must be removed contrary to the plain meaning of paragraph [0031]. Finally, regarding claim 21, Applicant asserts that Aboketaf does not disclose the orientation claimed therein. However, Examiner maintains that Aboketaf discloses a pad 20 having a second side edge, where STI region 24 and trench are disposed between the second side edge and first sidewall of layer 34 as shown in Figs. 5-6A. Fig. 5 shows most clearly that there are portions of STI region 24 that are disposed in the lateral dimension between the second side edge of the pad 20 and the first sidewall of layer 34. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Show 3 earlier events
Apr 03, 2026
Final Rejection mailed — §103
May 12, 2026
Interview Requested
May 18, 2026
Examiner Interview Summary
May 18, 2026
Applicant Interview (Telephonic)
May 19, 2026
Response after Non-Final Action
Jun 15, 2026
Request for Continued Examination
Jun 17, 2026
Response after Non-Final Action
Jul 30, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
81%
With Interview (+1.4%)
3y 6m (~3m remaining)
Median Time to Grant
High
PTA Risk
Based on 24 resolved cases by this examiner. Grant probability derived from career allowance rate.

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