DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-7, 9-12 and 16-22 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0115546 A1 to Aboketaf et al. (hereinafter “Aboketaf” – previously cited reference).
Regarding claim 1, Aboketaf discloses a structure for a photonics chip, the structure comprising:
a first dielectric layer (photonics chip structure 10 having dielectric layer 14; Fig. 2; paragraph [0025]);
a photodetector including a pad disposed on the first dielectric layer and a semiconductor layer positioned on the pad (photonics chip structure 10 having a photodetector including a photodetector pad 20 on layer 14 and having portions of germanium light-absorbing layer 34 disposed thereon; Figs. 6-6A; paragraphs [0001], [0025]-[0026], [0032]), the semiconductor layer having a first sidewall, the pad comprising a semiconductor material, and the pad including a top surface, a first trench that extends from the top surface partially through the pad toward the first dielectric layer, and a first side edge (layer 34 having first sidewall, pad 20 having semiconductor material, and pad 20 having top surface, side edge, and trench disposed therein from top surface towards layer 14; Figs. 6-6A; paragraphs [0025]-[0026], [0030]);
a waveguide core disposed on the first dielectric layer, the waveguide core including a tapered section adjacent to the first side edge of the pad (waveguide core 18 disposed over layer 14 and having tapered section adjacent side edge of pad 20; Figs. 5-6A; paragraph [0027]); and
a first confining feature in the pad, the first confining feature positioned adjacent to the first sidewall of the semiconductor layer, the first confining feature extending below the top surface of the pad, and the first confining feature comprising a dielectric material (first dielectric STI regions 24 disposed into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]).
Aboketaf fails to disclose forming a confining feature in the first trench of the pad.
However, Aboketaf already discloses the STI regions 24 being disposed in the pad 20 and in the same layer as the trench on adjacent opposing sides thereof as shown in Figs. 5-6A.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf in this manner in order to potentially provide improved electrical isolation within the trench, reduced parasitic effects within the trench, and better planarity and compatibility with further processing steps.
Regarding claim 2, Aboketaf discloses the structure of claim 1 wherein the semiconductor layer has a second sidewall opposite from the first sidewall, and further comprising: a second confining feature in the pad adjacent to the second sidewall of the semiconductor layer, the second confining feature extending below the top surface of the pad, and the second confining feature comprising the dielectric material (layer 34 having second sidewall opposite first sidewall and adjacent second dielectric STI region 24 disposed into top surface of pad 20; Figs. 5-6A; paragraph [0026]).
Regarding claim 3, Aboketaf discloses structure of claim 1 wherein the first trench has a uniform depth relative to the top surface (first dielectric STI region 24 disposed in trenches; Figs. 5-6A; paragraph [0026]).
Regarding claim 6, Aboketaf discloses the structure of claim 1 wherein the pad includes a second trench, the semiconductor layer is positioned in the second trench, and the first trench and the second trench extend to equal depths in the pad (first region 24 in a first trench in pad 20 and layer 34 disposed in a second trench in pad 20, where the first trench extends to the same depth as the second trench and beyond; Figs. 6-6A).
Regarding claim 7, Aboketaf discloses the structure of claim 1 wherein the pad includes a second trench, the semiconductor layer is positioned in the second trench, and the first trench and the second trench extend to unequal depths in the pad (first region 24 in a first trench in pad 20 and layer 34 disposed in a second trench in pad 20, where the first trench extends to the same depth as the second trench and beyond; Figs. 6-6A).
Regarding claim 9, Aboketaf discloses the structure of claim 1 wherein the pad includes a portion between the first confining feature and the semiconductor layer (pad 20 includes portion between first region 24 and layer 34; Figs. 6-6A).
Regarding claim 10, Aboketaf discloses the structure of claim 1 wherein the pad includes a doped region adjacent to the first sidewall of the semiconductor layer, and the first confining feature and the first trench are disposed in the doped region of the pad (pad 20 includes doped region 48, 50 adjacent first sidewall of layer 34 and first region 24 and trench disposed in doped region 48, 50; Figs. 6-6A).
Regarding claim 11, Aboketaf discloses the structure of claim 1 wherein the pad includes a second side edge opposite from the first side edge, and the first confining feature extends from the first side edge to the second side edge (pad 20 comprises second edge opposite the first edge where first region 24 extends horizontally from first to second edge; Fig. 5).
Regarding claim 12, Aboketaf discloses the structure of claim 1 wherein the first trench in the pad has a length that is oriented parallel to the first sidewall of the semiconductor layer (pad 20 has trench containing first region 24 with length parallel to first sidewall of layer 34; Figs. 6-6A).
Regarding claim 16, Aboketaf discloses the structure of claim 1 further comprising: a second dielectric layer that overlaps with the first confining feature (dielectric layer 26 overlapping with STI region 24; Fig. 4A; paragraph [0028]).
Regarding claim 17, Aboketaf discloses the structure of claim 16 further comprising: a third dielectric layer on the second dielectric layer; a doped region in the pad; and a contact extending through the second dielectric layer and the third dielectric layer to the doped region (middle-of-line (MOL) processing and back-end-of-line (BEOL) processing may be performed, which includes formation of silicide, contacts, vias, and wiring for an interconnect structure that is coupled with the photodetectors, in particular, separate sets of contacts may be formed in dielectric layers that respectively extend to the doped regions 48, 50; paragraph [0042]).
Regarding claim 18, Aboketaf discloses the structure of claim 17 wherein the first confining feature and the first trench are positioned in the doped region (STI region 24 and trench are positioned in doped region 48, 50 of pad 20; Figs. 7-7A).
Regarding claim 19, Aboketaf discloses the structure of claim 16 wherein the dielectric material of the first confining feature is silicon dioxide, and the second dielectric layer comprises silicon nitride (STI region 24 comprising silicon dioxide and dielectric layer 26 comprising silicon nitride; paragraphs [0026], [0028]).
Regarding claim 20, Aboketaf discloses a method of forming a structure for a photonics chip, the method comprising:
forming a photodetector that includes a pad disposed on a dielectric layer, wherein the pad comprises a semiconductor material (photonics chip structure 10 having a photodetector including a photodetector pad 20 on layer 14, where pad 20 has portions of germanium light-absorbing layer 34; paragraphs [0001], [0025]-[0026], [0032]);
forming a trench that extends from a top surface of the pad partially through the pad toward the dielectric layer (trench disposed within pad 20 and extending from top surface thereof towards layer 14; Figs. 6-6A; paragraphs [0025]-[0026], [0030]);
forming a semiconductor layer of the photodetector that is positioned on the pad (pad 20 having portions of germanium light-absorbing layer 34 disposed thereon; Figs. 6-6A; paragraphs [0001], [0025]-[0026], [0032]);
forming a waveguide core disposed on the dielectric layer, wherein the waveguide core includes a tapered section adjacent to a side edge of the pad (waveguide core 18 disposed over layer 14 and having tapered section adjacent side edge of pad 20; Figs. 5-6A; paragraph [0027]); and
forming a confining feature in the pad, wherein the confining feature is positioned adjacent to a sidewall of the semiconductor layer, the confining feature extends below the top surface of the pad, and the confining feature comprises a dielectric material (first dielectric STI regions 24 disposed into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]).
Aboketaf fails to disclose forming a confining feature in the trench of the pad.
However, Aboketaf already discloses the STI regions 24 being disposed in the pad 20 and in the same layer as the trench on adjacent opposing sides thereof as shown in Figs. 5-6A.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf in this manner in order to potentially provide improved electrical isolation within the trench, reduced parasitic effects within the trench, and better planarity and compatibility with further processing steps.
Regarding claim 21, Aboketaf discloses the structure of claim 1 wherein the pad includes a second side edge, and the first confining feature and the first trench are laterally positioned between the second side edge of the pad and the first sidewall of the semiconductor layer (pad 20 having second side edge with STI region 24 and trench disposed between the second side edge and first sidewall of layer 34; Figs. 6-6A).
Regarding claim 22, Aboketaf discloses the structure of claim 21 further comprising: a doped region in the pad, the doped region positioned between the second side edge of the pad and the first sidewall of the semiconductor layer (doped region 48, 50 of pad 20 disposed between second side edge of pad 20 and first sidewall of layer 34; Figs. 6-6A).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf in further view of US 10,241,269 B1 to Jacob et al. (hereinafter “Jacob” – previously cited reference).
Regarding claim 4, Aboketaf discloses the structure of claim 1 wherein the first trench has a first portion and a second portion, the first portion of the first trench is disposed adjacent to the first sidewall (first dielectric STI regions 24 disposed in trench into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]).
Aboketaf fails to disclose the first portion of the first trench has a shallower depth relative to the top surface than the second portion of the first trench.
However, Jacob discloses the first portion of the first trench has a shallower depth relative to the top surface than the second portion of the first trench (trench filled with dielectric material 22 and having first and second portions where first portion of trench is shallower to top surface of semiconductor structure 10a relative second portion of trench; abstract; Fig. 1; column 3, lines 11-53).
Aboketaf and Jacob are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Jacob in order to potentially provide compact polarization mode conversion, enhanced mode confinement and reduced crosstalk, and minimization of higher-order mode excitation and absorption losses.
Regarding claim 5, Aboketaf discloses the structure of claim 1 wherein the first trench has a first portion and a second portion, the first portion of the first trench is disposed adjacent to the first sidewall (first dielectric STI regions 24 disposed in trench into top surface of pad 20 adjacent sidewall of layer 34; Figs. 5-6A; paragraph [0026]).
Aboketaf fails to disclose the second portion of the first trench has a shallower depth relative to the top surface than the first portion of the first trench.
However, Jacob discloses the second portion of the first trench has a shallower depth relative to the top surface than the first portion of the first trench (trench filled with dielectric material 22 and having first and second portions where second portion of trench is shallower to top surface of semiconductor structure 10a relative first portion of trench; abstract; Fig. 1; column 3, lines 11-53).
Aboketaf and Jacob are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Jacob in order to potentially provide compact polarization mode conversion, enhanced mode confinement and reduced crosstalk, and minimization of higher-order mode excitation and absorption losses.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Aboketaf in view of US 2021/0191042 A1 to Peng et al. (hereinafter “Peng”).
Regarding claim 14, Aboketaf discloses the structure of claim 1. Aboketaf fails to disclose wherein the first confining feature comprises a metamaterial structure.
However, Peng discloses wherein the first confining feature comprises a metamaterial structure (metamaterial structures 116 disposed in alternating layers with insulating layers 118 therebetween in a horizontal stack; Fig. 1A; paragraphs [0028], [0033]-[0036]).
Aboketaf and Peng are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Peng in order to potentially provide improved mode confinement and reduced crosstalk, enhanced integration density, and low propagation loss and broadband operation.
Regarding claim 15, Aboketaf discloses the structure of claim 1. Aboketaf fails to disclose wherein the first confining feature comprises a first plurality of layers and a second plurality of layers that alternate with the first plurality of layers in a layer stack.
However, Peng discloses wherein the first confining feature comprises a first plurality of layers and a second plurality of layers that alternative with the first plurality of layers in a layer stack (metamaterial structures 116 disposed in alternating layers with insulating layers 118 therebetween in a horizontal stack; Fig. 1A; paragraphs [0028], [0033]-[0036]).
Aboketaf and Peng are both considered to be analogous to the claimed invention because they are in the same field of optical devices utilizing semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Aboketaf to incorporate the teaching of Peng in order to potentially provide improved mode confinement and reduced crosstalk, enhanced integration density, and low propagation loss and broadband operation.
Response to Arguments
Applicant’s arguments submitted January 26, 2026 have been fully considered. Specifically, Applicant substantively amended the independent claims, submitted corresponding statements that these amendments overcome the previous rejection, and added new claims 21-22. Examiner agrees that the amended independent claims overcome the previous 35 USC 102 rejection. However, a new ground of rejection of these claims necessitated by the amendments is presented. Further, Applicant’s assertion that Aboketaf does not disclose a trench that extends partially through the pad is not supported by Fig. 6A of Aboketaf as cited in this and the previous office action. Specifically, Fig. 6A clearly shows a trench being partially disposed through the pad 20, where the trench is completely filled with the body 36 of the layer 34.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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