DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 11 is objected to because of the following informalities: line 1 of claim 11 includes a typo by claiming dependency upon itself, claim 11, which is interpreted as being dependent upon claim 9 given the context of the original claim language. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the second dielectric layer deposited on the second epi layer” in lines 8-9, but ‘a second epi layer’ was introduced twice in connection with “a device wafer” and “a carrier wafer” which creates a lack of clarity as to which second epi layer is being referred to. Claims 2-7 depend from claim 1 and so are rejected on the same grounds.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 8 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0058617 A1 to Wu et al. (hereinafter “Wu” – previously cited reference).
Regarding claim 8, Wu discloses a wafer stack, comprising:
a first wafer component having a frontside and a backside, a second wafer component having a frontside and a backside, wherein the frontside of the second wafer component is bonded to the frontside of the first wafer component (IC dies 10, 20 having front and back sides, where dies 10, 20 are bonded together via front sides; Figs. 5 and 9; paragraphs [0009]-[0012], [0020]) and the second wafer component includes:
a substrate having a frontside layer and a backside layer positioned between the frontside and the backside thereof (IC die 20 having front and back sides with back side layer therebetween; Fig. 9);
a frontside first dielectric layer disposed on the substrate, wherein at least one first metal layer component is disposed therein (plurality of metal lines 206 where at least one of the is disposed within dielectric layer 210 on front side of substrate 200; Fig. 9; paragraph [0013]);
a backside second dielectric layer disposed on the substrate, wherein at least one second metal layer component is disposed therein (bonding dielectric layer 220 disposed on back side of substrate 200 having plurality of metal lines 206 including bonding metal line 236 and bonding metal via 238 disposed therein; Fig. 9; paragraph [0017]);
at least one via contacting the at least one frontside first metal layer component and the at least one backside second metal layer component through the substrate (TSV 218 contacting front and back side metal lines through substrate 200; Fig. 9); and
at least one transistor positioned on the backside layer of the substrate and contacting the at least one second metal layer component disposed in the backside second dielectric layer (semiconductor devices 102 may be transistors disposed in bottom half of die 20 and in electrical contact with the plurality of metal lines 206 including bonding metal line 236 and bonding metal via 238; Fig. 9; paragraphs [0016], [0027]); and
a third wafer component having a frontside and a backside, wherein the frontside of the third wafer component is bonded to the backside of the second wafer component (IC die 30 having front and back side and front side of die 30 bonded to back side of die 20; Figs. 5 and 9; paragraphs [0009]-[0012], [0020]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9 and 11-21 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in further view of US 2021/0098381 A1 to Yu et al. (hereinafter “Yu” – previously cited reference).
Regarding claim 9, Wu discloses the wafer stack of claim 8, wherein at least one photodiode is formed on the backside of the first wafer component (semiconductor device 102 may include one or more diodes formed in lower half of die 10; Fig. 9; paragraph [0027]).
Wu fails to disclose wherein the first wafer component is a system on chip.
However, Yu discloses wherein the first wafer component is a system on chip d(integrated circuit components 130, 200 which may be bonded together and may be implemented as system-on-a-chip and application-specific integrated circuits; Fig. 1; paragraphs [0040]-[0041], [0061]).
Wu and Yu are both considered to be analogous to the claimed invention because they are in the same field of bonded wafer stacks. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wu to incorporate the teaching of Yu in order to potentially provide optimized I/O and external connectivity, enhanced intra-stack bandwidth and low latency, efficient power delivery network, and improved thermal management.
Regarding claim 11, as best understood, Wu in view of Yu discloses the wafer stack of claim 9. Wu further discloses further comprising at least one metal-insulator-metal component electrically contacting the at least one transistor (semiconductor devices 102 may also include a MIM capacitor that is in electrical contact with the other devices 102 which may include the transistor; Fig. 9; paragraphs [0016], [0027]).
Regarding claim 12, Wu in view of Yu discloses the wafer stack of claim 11. Wu further discloses wherein the at least one transistor is a three-dimensional transistor or a planar transistor (semiconductor device 102 may be a MOSFET which is a planar transistor; paragraph [0016]).
Regarding claim 13, Wu in view of Yu discloses the wafer stack of claim 12. Wu further discloses wherein the first wafer component further comprises: a substrate having a frontside surface and backside surface (first die 10 having substrate 100 with front and back side surface; Fig. 9); a third dielectric layer on the frontside surface (dielectric layer 110 on front side of substrate 100; Fig. 9; paragraph [0013]); at least one third metal layer component disposed in the third dielectric layer (plurality of metal lines 108 disposed within dielectric layer 110; Fig. 9; paragraph [0013]); a first anchor layer formed on the third dielectric layer (bonding dielectric layer 120 disposed upon layer 110; Figs. 9 and 15; paragraph [0027]); and at least one first redistribution layer component extending through the first anchor layer to the at least one third metal layer component disposed in the third dielectric layer (bonding contact 112 and redistribution layer 114 extending through layer 120 to metal lines 106 in layer 110; Figs. 9 and 15; paragraph [0027]).
Regarding claim 14, Wu in view of Yu discloses the wafer stack of claim 13. Wu further discloses wherein the first wafer component further comprises: at least one transistor positioned on the at least one third metal layer component (semiconductor devices 102 may be transistors in electrical contact with the plurality of metal lines 206; Fig. 9; paragraphs [0016], [0027]), and at least one metal-insulator-metal component electrically contacting the at least one transistor (semiconductor devices 102 may also include a MIM capacitor that is in electrical contact with the other devices 102 which may include the transistor; Fig. 9; paragraphs [0016], [0027]), wherein the at least one transistor is a three-dimensional transistor or a planar transistor (semiconductor device 102 may be a MOSFET which is a planar transistor; paragraph [0016]).
Regarding claim 15, Wu in view of Yu discloses the wafer stack of claim 13. Wu further discloses wherein the third wafer component further comprises: a substrate having a frontside surface and backside surface (third IC die 30 having substrate 300 with front and back surfaces; Fig. 9; paragraph [0020]); a fourth dielectric layer on the frontside surface (dielectric layer 310 disposed on front surface of substrate 300; Fig. 9; paragraph [0020]); at least one fourth metal layer component disposed in the fourth dielectric layer (metal lines 306 disposed in layer 310; Fig. 9); a second anchor layer formed on the fourth dielectric layer (bonding dielectric layer 320 disposed on layer 310; Fig. 9; paragraph [0020]); and at least one second redistribution layer component extending through the second anchor layer to the at least one fourth metal layer component disposed in the fourth dielectric layer (redistribution layer 324 disposed through layer 320 to metal lines 306; Fig. 12; paragraph [0023]).
Regarding claim 16, Wu in view of Yu discloses the wafer stack of claim 15. Wu further discloses wherein the third wafer component further comprises: at least one transistor positioned on the at least one fourth metal layer component (semiconductor devices 102 may be transistors in electrical contact with the plurality of metal lines 306; Fig. 9; paragraphs [0016], [0027]), and at least one metal-insulator-metal component electrically contacting the at least one transistor (semiconductor devices 102 may also include a MIM capacitor that is in electrical contact with the other devices 102 which may include the transistor; Fig. 9; paragraphs [0016], [0027]), wherein the at least one transistor is a three-dimensional transistor or a planar transistor (semiconductor device 102 may be a MOSFET which is a planar transistor; paragraph [0016]).
Regarding claim 17, Wu in view of Yu discloses the wafer stack of claim 15. Wu further discloses wherein the second wafer component further comprises: a frontside third anchor layer formed on the frontside first dielectric layer (top surface portion of silicon nitride dielectric layer 210 in bonding structure 132 disposed on remainder of layer 210; Figs. 5 and 9; paragraphs [0009]-[0012]); a backside fourth anchor layer formed on the backside second dielectric layer (top surface portion of silicon nitride dielectric layer 220 in bonding structure 332 disposed on remainder of layer 220; Figs. 5 and 9; paragraphs [0009]-[0012]); at least one frontside third redistribution layer component extending through the frontside third anchor layer to the at least one first metal layer component disposed in the frontside dielectric layer (redistribution layer 214 extending through top surface portion of silicon nitride dielectric layer 210 to the metal lines 206; Figs. 5 and 9; paragraphs [0009]-[0012]); and at least one backside fourth redistribution layer component extending through the backside fourth anchor layer to the at least one second metal layer component disposed in the backside second dielectric layer (redistribution layer 224 extending through top surface portion of silicon nitride dielectric layer 220 to the plurality of metal lines 206 including bonding metal line 236 and bonding metal via 238; Figs. 5 and 9; paragraphs [0009]-[0012]).
Regarding claim 18, Wu in view of Yu discloses the wafer stack of claim 15. Wu further discloses wherein: the at least one first redistribution layer component of the first wafer component is bonded to the at least one frontside third redistribution layer component of the second wafer component forming a first hybrid bond therebetween (layers 114, 214 bonded together along with layers 110, 210 bonded together in hybrid bonding; Figs. 5 and 9; paragraphs [0009]-[0012]); and the at least one second redistribution layer component of the third wafer component is bonded to the at least one backside fourth redistribution layer component of the second wafer component forming a second hybrid bond therebetween (layers 214, 314 bonded together along with layers 210, 310 bonded together in hybrid bonding; Figs. 5 and 9; paragraphs [0009]-[0012]).
Regarding claim 19, Wu discloses a method of forming a wafer stack, comprising:
forming a first wafer component comprising: forming at least one first metal layer component on a first wafer substrate, the first wafer substrate having a frontside layer and a backside layer, and the first wafer substrate positioned between a frontside of the first wafer component and a backside of the first wafer component, wherein the at least one first metal component is formed on the frontside of the first wafer substrate (3D IC formed by stacking wafer, metal lines 206 are formed on front side of IC die 20 having substrate 200 with front and back sides; Fig. 5; paragraph [0013]), depositing a frontside first dielectric layer on the frontside layer of the first wafer substrate, forming a frontside first anchor layer on the frontside dielectric layer, and forming at least one first redistribution layer component contacting the at least one first metal layer component and extending through the frontside first anchor layer (silicon nitride dielectric layer 210 formed on front side of substrate 200, top surface portion of layer 210 in first bonding structure 132 disposed on remainder of layer 210, and redistribution layer 214 extending through top surface portion and contacting metal lines 206; Fig. 5; paragraph [0013]);
bonding a frontside of a wafer component to the first anchor layer of the first wafer component (front side of IC die 10 bonded to top surface portion of layer 210 of front side of IC die 20; Fig. 5);
forming at least one second metal layer component on the backside layer of the first wafer substrate subsequent to bonding with the wafer component (plurality of metal lines 206 including bonding metal line 236 and bonding metal via 238 disposed on backside of substrate 200; Fig. 5; paragraph [0017]);
depositing a backside second dielectric layer on the first wafer substrate (silicon nitride bonding dielectric layer 220 disposed on back side of substrate 200; Fig. 5; paragraphs [0013], [0017]);
forming a backside second anchor layer on the backside second dielectric layer, forming at least one second redistribution layer component contacting the at least one second metal layer component and extending through the backside second anchor layer (top surface portion silicon nitride layer 220 disposed on remainder of layer 220 and redistribution layer 224 extending through layer 220 to contact plurality of metal lines 206 including bonding metal line 236 and bonding metal via 238; Fig. 5; paragraph [0017]); and
bonding a frontside of a second wafer component to the backside second anchor layer of the first wafer component (front side of IC die 30 bonded to back side of top surface of layer 220 of IC die 20; Figs. 5 and 9; paragraphs [0009]-[0012]).
Wu fails to disclose the first and second wafer components being an ASIC component, the first substrate being an SOI substrate, and the wafer component being a system on chip component.
However, Yu discloses the first and second wafer components being an ASIC component, the first substrate being an SOI substrate, and the wafer component being a system on chip component (integrated circuit components 130, 200 which may be bonded together and may be implemented as system-on-a-chip and application-specific integrated circuits utilizing a SOI substrate; Fig. 1; paragraphs [0040]-[0041], [0061], [0185]).
Wu and Yu are both considered to be analogous to the claimed invention because they are in the same field of bonded wafer stacks. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wu to incorporate the teaching of Yu in order to potentially provide optimized I/O and external connectivity, enhanced intra-stack bandwidth and low latency, efficient power delivery network, and improved thermal management.
Regarding claim 20, Wu in view of Yu discloses the method of claim 19. Wu further discloses wherein the frontside of the wafer component further comprises a third anchor layer and at least one third redistribution layer component extending therethrough (front side of IC die 10 having top surface portion of dielectric layer 110 in first bonding structure 132 and redistribution layer 114 extending through layer 110; Fig. 5; paragraph [0013]); the frontside of the second wafer component further comprises a second wafer component fourth anchor layer and at least one fourth redistribution layer component extending therethrough (front side of IC die 20 comprises top surface portion of silicon nitride dielectric layer 210 which has redistribution layer 214 extending therethrough; Fig. 5; paragraph [0013]); the at least one third redistribution layer component of the wafer component is bonded to the at least one frontside first redistribution layer component of the first wafer component forming a first hybrid bond therebetween (layers 114, 214 bonded together along with layers 110, 210 bonded together in hybrid bonding; Figs. 5 and 9; paragraphs [0009]-[0012]); and the at least one fourth redistribution layer component of the second wafer component is bonded to the at least one backside second redistribution layer component of the first wafer component forming a second hybrid bond therebetween (layers 214, 314 bonded together along with layers 210, 310 bonded together in hybrid bonding; Figs. 5 and 9; paragraphs [0009]-[0012]).
Wu fails to disclose the first and second wafer components being an ASIC component and wafer component being a system on chip component.
However, Yu discloses the first and second wafer components being an ASIC component and wafer component being a system on chip component (integrated circuit components 130, 200 which may be bonded together and may be implemented as system-on-a-chip and application-specific integrated circuits; Fig. 1; paragraphs [0040]-[0041], [0061]).
Wu and Yu are both considered to be analogous to the claimed invention because they are in the same field of bonded wafer stacks. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Wu to incorporate the teaching of Yu in order to potentially provide optimized I/O and external connectivity, enhanced intra-stack bandwidth and low latency, efficient power delivery network, and improved thermal management.
Regarding claim 21, Wu in view of Yu discloses the method of claim 20. Wu further discloses forming at least one transistor on a backside of the second ASIC wafer component (semiconductor devices 102 may be transistors disposed in bottom half of die 20 on backside of substrate 200; Fig. 4; paragraphs [0016], [0027]).
Response to Arguments
Applicant's arguments filed February 4, 2026 have been fully considered. Applicant submitted amendments to the claims and corresponding arguments. Examiner agrees that most of the 35 USC 112 rejections have been overcome but for those outlined above. However, Examiner disagrees that these amendments have overcome all of the 35 USC 102 and 103 rejections. While amended claim 1 would be allowable but for the 35 USC 112 rejection, amended independent claims 8 and 19 do not overcome the previous rejections. Amended claim 8 incorporates the contents of canceled claim 10 which was disclosed by Wu and Applicant does not substantively argue that point. Amended claim 19 was not substantively amended to a degree that it overcomes the previous 35 USC 103 rejection using Wu and Yu as outlined above. New claim 21 recites content that was disclosed by Wu in the previous office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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