DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8, 11, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 8 and 16 recite the limitation “high-speed laser pulses”. There is insufficient antecedent basis for this limitation in the claims. The Examiner suggests amending the claims to read “laser pulses” instead.
Claim 11 recites the limitation "the each lead frame unit" in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claims depending from the rejected claims noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 10-13, 15, and 21-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abbott (US 2012/0009739).
Regarding claim 1, Abbot discloses a lead frame (Figure 1-6) comprising:
a plurality of lead frame units (para. [0033] discloses leadframes, and see Figure 2, which shows one lead frame unit, however it is well-known in the art that multiple lead frame units are fabricated together with one outer frame and later singulated to form individual semiconductor packages), each lead frame unit (200) of the plurality of lead frame units including:
at least one pin (lead segments 111);
a first soldering region (112, see Figures 1-3) on the at least one pin (111) and comprising no roughened surface (para. [0024] discloses 112 having a smooth surface); and
a non-soldering region (114) on the at least one pin (111) and comprising a roughened surface (see para. [0029] which discloses roughing the surface of region 114), wherein the non-soldering region (114) is located closer to a cutting line of the each lead frame unit (200) than the first soldering region (112, Figure 1 shows the cutting line at the outer ends of each pin 111, and the non-soldering region 114 is closer in proximity to the cutting line than the soldering region 112 is).
Regarding claim 2, Abbott discloses wherein the each lead frame unit (200) of the plurality of lead frame units further includes:
a base island (110) with the at least one pin (111) arranged around the base island (110, see Figures 1 and 2), and
a second soldering region (113) arranged on the base island (110, see Figures 1 and 2).
Regarding claim 3, Abbott discloses wherein the first soldering region (112) is electrically connectable to a chip (101, see bond wire connection at 112 to the chip 101 in Figure 1).
Regarding claim 4, Abbott discloses wherein the first soldering region (112) and the second soldering region (113) are electrically connectable to a chip (101, the first soldering region 112 is electrically connected to the chip 101, and the second soldering region 113 of the base island is capable of having electrical connection to the chip due to its electrically conductive material, since the chip pad/base island 110 is part of the metallic lead frame, and the soldering region 113 is a region of the lead frame itself).
Regarding claim 6, Abbott further discloses an outer frame (201) arranged around the plurality of lead frame units (see Figure 2, which shows one lead frame unit, however it is well-known in the art that multiple lead frame units are fabricated together with one outer frame and later singulated to form individual semiconductor packages), wherein each of the plurality of lead frame units further includes a plurality of connecting ribs (dam bar 203), the plurality of connecting ribs (203) correspond to a plurality of pins (111), and each of the plurality of connecting ribs (203) is configured to connect the outer frame (201) with a corresponding pin of the plurality of pins (111, see Figure 2).
Regarding claim 7, Abbott discloses wherein the roughened surface (surface of 114) of the non-soldering region (114) comprises ablation slots (made by laser pulses, see para. [0029]), and the ablation slots are generated using laser pulses (see para. [0029] which discloses using pulsed beams of light to roughen the surface of the lead frame).
Regarding claim 10, Abbot discloses a package (Figure 1-6) comprising:
a lead frame (200) comprising a plurality of lead frame units (para. [0033] discloses leadframes, and it is well known in the art that lead frame package units are fabricated together on one frame and later singulated to form individual lead frame package units), each lead frame unit (200) of the plurality of lead frame units including:
a plurality of pins (111, see Figures 1-2);
a first soldering region (112) located on each pin (111) of the plurality of pins (111) and comprising no roughened surface (para. [0024] discloses 112 having a smooth surface); and
a non-soldering region (114) located on the each pin (111) of the plurality of pins (111, see Figures 1-2) and comprising a roughened surface (see para. [0029] which discloses roughing the surface of region 114), wherein the non-soldering region (114) is located closer to a cutting line of the each lead frame unit (200) than the first soldering region (112, Figure 1 shows the cutting line at the outer ends of each pin 111, and the non-soldering region 114 is closer in proximity to the cutting line than the soldering region 112 is);
wherein the lead frame (200) is packaged (see Figure 1) using the roughened surface (of 114) to form a locking structure (see para. [0028]).
Regarding claim 11, Abbott discloses wherein the each lead frame unit (200) of the plurality of lead frame units further includes:
a base island (110) with the plurality of pins (111) arranged around the base island (110, see Figures 1-2), and
a second soldering region (113) arranged on the base island (110, see Figures 1 and 2).
Regarding claim 12, Abbott discloses wherein the first soldering region (112) and the second soldering region (113) are electrically connectable to a chip (101, the first soldering region 112 is electrically connected to the chip 101, and the second soldering region 113 of the base island is capable of having electrical connection to the chip due to its electrically conductive material, since the chip pad/base island 110 is part of the metallic lead frame, and the soldering region 113 is a region of the lead frame itself, thus is electrically connectable to the chip).
Regarding claim 13, Abbott discloses wherein the first soldering region (112) is electrically connectable to a chip (101, see bond wire connection at 112 to the chip 101 in Figure 1).
Regarding claim 15, Abbott discloses wherein the roughened surface (surface of 114) of the non-soldering region (114) comprises ablation slots (made by laser pulses, see para. [0029]), and the ablation slots are generated using laser pulses (see para. [0029] which discloses using pulsed beams of light to roughen the surface of the lead frame).
Regarding claim 21, Abbott discloses a lead frame (Figures 1-6) comprising a plurality of lead frame units (see Figure 2, which shows one lead frame unit, however it is well-known in the art that multiple lead frame units are fabricated together with one outer frame and later singulated to form individual semiconductor packages), each lead frame unit (200) of the plurality of lead frame units comprises:
a base island (110);
a plurality of pins (111) around the base island (see Figures 1-2);
a soldering region (112) on each pin (111) of the plurality of pins (111) and comprising no roughened surface (para. [0024] discloses 112 having a smooth surface);
a non-soldering region (114) on the each pin (111) of the plurality of pins (111, see Figures 1-2) and comprising a roughened surface (see para. [0029] which discloses roughing the surface of region 114), wherein the non-soldering region (114) is located closer to a cutting line of the each lead frame unit than the soldering region (112, Figure 1 shows the cutting line at the outer ends of each pin 111, and the non-soldering region 114 is closer in proximity to the cutting line than the soldering region 112 is).
Regarding claim 22, Abbott discloses wherein the soldering region (112) is electrically connectable to a chip (101, see bond wire connection at 112 to the chip 101 in Figure 1).
Regarding claim 23, Abbott discloses an outer frame (201) arranged around the plurality of lead frame units (see Figure 2), the outer frame (201) being connected to the plurality of pins (111, see Figure 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Abbott (US 2012/0009739).
Regarding claim 8, Abbott discloses wherein the high-speed laser pulses are generated by a laser emitter (see para. [0029]) that has power in a range from 290 watts to 300 watts (under 10W, see para. [0029]), and a wavelength of the high-speed laser pulses is in a range from 530 nanometer (nm) to 535 nm (visible or infrared light, which is within the claimed range of 530-535nm wavelength, which is within the visible green light wavelengths).
Although the prior art discloses a power range of a maximum of 10W, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Additionally, Abbott contemplate selecting the power of the laser according to manufacturing requirements, see Abbot, para. [0029]).
The Examiner further notes that claim 8 is a product-by-process claim, thus determination of patentability is based on the product itself. See MPEP 2113.
Regarding claim 9, Abbott discloses wherein a depth of the ablation slots (recesses of roughened surface, para. [0029]) is in a range from 0.035 mm (millimeter) to 0.05 mm (para. [0010] discloses that the ablation slots are about 20 to 30 microns deep).
Although the prior art discloses a depth of the ablation slots of about 20 to 30 microns, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Regarding claim 16, Abbott discloses wherein the high-speed laser pulses are generated by a laser emitter (see para. [0029]) that has power in a range from 290 watts to 300 watts (under 10W, see para. [0029]), and a wavelength of the high-speed laser pulses is in a range from 530 nanometer (nm) to 535 nm (visible or infrared light, which is within the claimed range of 530-535nm wavelength, which is within the visible green light wavelengths).
Although the prior art discloses a power range of a maximum of 10W, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art. Additionally, Abbott contemplate selecting the power of the laser according to manufacturing requirements, see Abbot, para. [0029]).
The Examiner further notes that claim 16 is a product-by-process claim, thus determination of patentability is based on the product itself. See MPEP 2113.
Regarding claim 17, Abbott discloses wherein a depth of the ablation slots (recesses of roughened surface, para. [0029]) is in a range from 0.035 mm (millimeter) to 0.05 mm (para. [0010] discloses that the ablation slots are about 20 to 30 microns deep).
Although the prior art discloses a depth of the ablation slots of about 20 to 30 microns, it has been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Abbott as applied to claims 1 and 10, respectively, above, and further in view of Sonehara et al. (“Sonehara” US 2019/0157196).
Regarding claim 5, Abbot does not disclose flip-chip bonding, since the chip 101 is electrically connected using wire bonding, see Figure 1.
Sonehara, however, discloses an alternative chip bonding technique to wire bonding, i.e. flip chip bonding, see Figures 1B and 11B, and discloses in Figure 1B that first soldering region (region occupied by 23) is provided with at least one soldering pad (23 is a plating layer, which is construed as a pad), to which a chip (12) is attachable using flip-chip soldering (see Figure 1B and para. [0041]).
All of the claimed elements are evidenced as known in Abbott except for the specific type of chip attachment design. One of ordinary skill in the art would have recognized the finite number of predictable solutions for electrically and physically connected a chip to a surface as evidenced by Sonehara, namely, either flip-chip bonding or die attachment bonding. Absent unexpected results, it would have been obvious to try each of the two different attachment designs to yield a suitable attachment for providing electrical connection and physical attachment to a chip. Additionally, it would have been obvious to one having ordinary skill in the art to incorporate the flip-chip bonding as taught by Sonehara into the teachings of Abbott because substituting one known element (flip-chip attachment) for another known equivalent element (wire connections) resulting in the predictable result of forming electrical connection for the chip. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 14, Abbot does not disclose flip-chip bonding, since the chip 101 is electrically connected using wire bonding, see Figure 1.
Sonehara, however, discloses an alternative chip bonding technique to wire bonding, i.e. flip chip bonding, see Figures 1B and 11B, and discloses in Figure 1B that first soldering region (region occupied by 23) is provided with at least one soldering pad (23 is a plating layer, which is construed as a pad), to which a chip (12) is attachable using flip-chip soldering (see Figure 1B and para. [0041]).
All of the claimed elements are evidenced as known in Abbott except for the specific type of chip attachment design. One of ordinary skill in the art would have recognized the finite number of predictable solutions for electrically and physically connected a chip to a surface as evidenced by Sonehara, namely, either flip-chip bonding or die attachment bonding. Absent unexpected results, it would have been obvious to try each of the two different attachment designs to yield a suitable attachment for providing electrical connection and physical attachment to a chip. Additionally, it would have been obvious to one having ordinary skill in the art to incorporate the flip-chip bonding as taught by Sonehara into the teachings of Abbott because substituting one known element (flip-chip attachment) for another known equivalent element (wire connections) resulting in the predictable result of forming electrical connection for the chip. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s amendments with respect to the objection to claim 22 have been fully considered and overcome the objection. The objection to claim 22 has been withdrawn.
Applicant’s amendments with respect to the 112(b) rejections of claims 1, 7, 10, 15, and 21 have been fully considered and overcome the 112(b) rejections. The 112(b) rejections of claim 1, 7, 10, 15, and 21 have been withdrawn.
Applicant’s arguments regarding claims 1, 10, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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