Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 9 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2020/0388600, as recited in previous Office Action) in view of Kang et al. (US 2016/0037620).
As for claim 1, Huang et al. disclose in Fig. 1 and the related text a semiconductor device, comprising:
a core 12/12C/13/14a/15a having a first (upper) surface and a second (lower) surface;
a first build-up structure 14a/15a/14a1/30 formed on the first surface and comprising a plurality of first build-up conductive portions 14a/14a1; and
an input/output conductive structure 40 formed above the first build-up structure and comprising a plurality of input/output conductive portions 421/42V;
wherein an input/output line width/line spacing (L/S) of the input/output conductive portions 421/42V is different from a first L/S of the first build-up conductive portions 14a/14a1(Fig. 1).
Huang et al. do not disclose the core comprising a clad element formed of a thermal conductive material.
Kang et al. teach in Figs. 1-3 and the related text a core 110/121/122 comprising a clad element 150 formed of a thermal conductive material [0031].
Huang et al. and Kang et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Huang et al. to include the limitations as taught by Kang et al., in order to provide heat dissipation (Huang et al. ¶0024).
As for claim 2, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the first build-up structure 14a/15a/14a1/30 is formed on the first surface of the core (Fig. 1), and the semiconductor device further comprises:
a second build-up structure 14b/15b/16 is formed on the second surface of the core and comprising a plurality of second build-up conductive portions 14b/16a;
wherein the input/output L/S or a second L/S of the second build-up conductive portions is different from the first L/S of the first build-up conductive portions (Fig. 1).
As for claim 3, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the input/output L/S of the first input/output conductive portions 421/42V is smaller than the first L/S of the first build-up conductive portions 14a/14a1 (Fig. 1, [0039]).
As for claim 4, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the input/output conductive structure 40 is a wafer-level or a panel-level fanout RDL (redistribution layers) structure or a wafer BEOL (back- end-of-line) structure [0030].
As for claim 5, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the first build-up structure 14a/15a/14a1/30 is located between the core and the input/output conductive structure (Fig. 1).
As for claim 6, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the semiconductor device further comprises a second build-up structure 14b/15b formed on the second surface of the core (Fig. 1), and the core further comprises: a plurality of dielectric layers 12/15a/15b stacked on each other (Fig. 1); and a plurality of conductive vias 13 passing through the dielectric layers and electrically connecting the first build-up structure 30/14a1 and the second build-up structure 16 (Fig. 1).
As for claim 7, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the semiconductor device further comprises a second build-up structure 14b/15b formed on the second surface of the core (Fig. 1)the core further comprises: a plurality of clad metal blocks 14a or a clad metal plate with openings or cavities; an insulation layer 12/12C enclosing the clad metal blocks; and a plurality of conductive vias 13 passing through the insulation layer and electrically connecting the first build-up structure 14a1/30 and the second build-up structure 16 (Fig. 1).
As for claim 9, Huang et al. disclose the semiconductor device claimed in claim 1, except the minimal input/output L/S of the input/output conductive portions ranges between 1 micrometers (µm) and 5 µm.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the minimal input/output L/S of the input/output conductive portions ranges between 1 micrometers (µm) and 5 µm, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
As for claim 15, Huang et al. disclose the semiconductor device claimed in claim 1, further comprising: a semiconductor chip 20 embedded in in the core (Fig. 1).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in view of Kang et al. and further in view Wu et al. (US 2023/0060716).
As for claim 12, Huang et al. disclose the semiconductor device claimed in claim 1, further comprising:
an interposer 52/53 disposed on the input/output conductive structure (Fig. 1);
at least one memory component (left 50) [0021] disposed on the interposer; and a component (right 50) disposed on the interposer (Fig. 1);
wherein the at least one memory component and the component are disposed side-by-side (Fig. 1).
Huang et al. do not disclose the component is a processor.
Wu et al. teach in Fig. 1 and the related text a processor disposes on an interposer and next to memory component [0016].
Huang et al. and Wu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Huang et al. to include the limitations as taught by Wu et al., in order to provide functionalities of the device [0001].
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811
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