Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I Species C(d) (Figs. 4 and 8, claims 1-7, 9, 12 and 15) in the reply filed on 01/28/2026 is acknowledged.
Claims 8, 10, 11, 13, 14 and 16-22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/28/2026.
Claims 10 and 13 is have been withdrawn from further consideration because claim 10 recites the limitation “a cold plate” which is drawn to Embodiment of Figs. 6-7 which belong to different species, and claim 13 recites the limitation “a memory component mounted on top of each processor” which is drawn to Embodiment of Fig. 9 which belong to different species.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/29/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9, 12 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 3 recited the claimed limitations of "and/or", are unclear as to which structure is claimed.
Claim 1 line 7 recited the claimed limitations of "an input/output line width/line spacing", are unclear as to what applicant mean by an input/output line width/line spacing? Also, width/line is unclear as to which structure is claimed.
Claim 2 line 6, claim 3 line 1 recites the limitation "the input/output L/S". There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2020/0388600).
As for claim 1, Huang et al. disclose in Fig. 1 and the related text a semiconductor device, comprising:
a core 12/12C/13/14a/15a having a first (upper) surface and a second (lower) surface;
a first build-up structure 14a/15a/14a1/30 formed on the first surface and/or the second surface and comprising a plurality of first build-up conductive portions 14a/14a1; and
an input/output conductive structure 40 formed above the first build-up structure and comprising a plurality of input/output conductive portions 421/42V;
wherein an input/output line width/line spacing (L/S) of the input/output conductive portions 421/42V is different from a first L/S of the first build-up conductive portions 14a/14a1(Fig. 1).
As for claim 2, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the first build-up structure 14a/15a/14a1/30 is formed on the first surface of the core (Fig. 1), and the semiconductor device further comprises:
a second build-up structure 14b/15b/16 is formed on the second surface of the core and comprising a plurality of second build-up conductive portions 14b/16a;
wherein the input/output L/S or a second L/S of the second build-up conductive portions is different from the first L/S of the first build-up conductive portions (Fig. 1).
As for claim 3, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the input/output L/S of the first input/output conductive portions 421/42V is smaller than the first L/S of the first build-up conductive portions 14a/14a1 (Fig. 1, [0039]).
As for claim 4, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the input/output conductive structure 40 is a wafer-level or a panel-level fanout RDL (redistribution layers) structure or a wafer BEOL (back- end-of-line) structure [0030].
As for claim 5, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the first build-up structure 14a/15a/14a1/30 is located between the core and the input/output conductive structure (Fig. 1).
As for claim 6, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the core comprises: a plurality of dielectric layers 12/15a/15b stacked on each other (Fig. 1); and a plurality of conductive vias 13 passing through the dielectric layers and electrically connecting the first build-up structure 30/14a1 and the second build-up structure 16 (Fig. 1).
As for claim 7, Huang et al. disclose the semiconductor device claimed in claim 1, wherein the core comprises: a plurality of clad metal blocks 14a or a clad metal plate with openings or cavities; an insulation layer 12/12C enclosing the clad metal blocks; and a plurality of conductive vias 13 passing through the insulation layer and electrically connecting the first build-up structure 14a1/30 and the second build-up structure 16 (Fig. 1).
As for claim 15, Huang et al. disclose the semiconductor device claimed in claim 1, further comprising: a semiconductor chip 20 embedded in in the core (Fig. 1).
Claim Rejections - 35 USC § 103
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al..
As for claim 9, Huang et al. disclose the semiconductor device claimed in claim 1, except the minimal input/output L/S of the input/output conductive portions ranges between 1 micrometers (µm) and 5 µm.
It would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the minimal input/output L/S of the input/output conductive portions ranges between 1 micrometers (µm) and 5 µm, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. in view of Wu et al. (US 2023/0060716).
As for claim 12, Huang et al. disclose the semiconductor device claimed in claim 1, further comprising:
an interposer 52/53 disposed on the input/output conductive structure (Fig. 1);
at least one memory component (left 50) [0021] disposed on the interposer; and a component (right 50) disposed on the interposer (Fig. 1);
wherein the at least one memory component and the component are disposed side-by-side (Fig. 1).
Huang et al. do not disclose the component is a processor.
Wu et al. teach in Fig. 1 and the related text a processor disposes on an interposer and next to memory component [0016].
Huang et al. and Wu et al. are analogous art because they both are directed packaging devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Huang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Huang et al. to include the limitations as taught by Wu et al., in order to provide functionalities of the device [0001].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG Q TRAN whose telephone number is (571)270-3259. The examiner can normally be reached on Monday-Thursday (9am-4pm).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 5712721670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TRANG Q TRAN/Primary Examiner, Art Unit 2811