DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I (claim 1-18 and 21-22) in the reply filed on 11/07/2025 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Müller; Stefan Ferdinand (US PGpub: 2022/0376114 A1), hereinafter Müller, in view of HEO et al. (US Pgpub: 2021/0359101 A1), hereinafter HEO.
Regarding claim 1, Müller teaches a field-effect transistor (FET) device selectively switchable between a first state and a second state, the FET comprising:
source (302sd) and drain (302sd) regions;
a channel region (302) disposed between the source and drain regions;
a gate (314) arranged to selectively receive a bias voltage to selectively switch the FET between the first state and the second state;
a memory structure (306 and other layers) disposed between the gate and the channel region,
Müller does not explicitly teach the memory structure including a first portion which is anti-ferroelectric and a second portion which is ferroelectric (310) , the first and second portions being polarized in a first direction when the FET is in the first state and at least one depolarization dielectric layer disposed proximate to the memory structure.
However, HEO teaches the memory structure including a first portion which is anti-ferroelectric (230) and a second portion which is ferroelectric (220) , the first and second portions being polarized in a first direction when the FET is in the first state and at least one depolarization dielectric layer (210) disposed proximate to the memory structure (Paragraph [0059]). Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use Müller’s FET to modify with teachings from HEO in order to obtain a FeRAM that has multiple logic states and spontaneous polarization of ferroelectrics may be maintained.
Regarding claim 2, Müller teaches the FET device of claim 1, wherein, when the FET is set to the first state, the at least one depolarization dielectric layer (304 in FIG. 3A and 024 in FIG. 1)) operates to destabilize a polarization of at least the second portion of the memory structure while maintaining a polarization of the first portion of the memory structure (Paragraph [0028]-[0032]).
Regarding claim 3, Müller teaches the FET device of claim 2, wherein the at least one depolarization dielectric layer operates to destabilize the polarization of at least the second portion of the memory structure by creating an electric field in a direction opposite the first direction (Paragraph [0028]-[0032]).
Regarding claim 13, Müller teach the FET device of claim 1, wherein the at least one depolarization dielectric layer (304 in FIG. 6) is disposed between the memory structure and the gate.
Regarding claim 15, Müller teach a three-dimensional memory array comprising:
a metallization including patterned metal layers spaced apart by intermetal dielectric material (IMD) (330) and interlayer vias passing through the IMD and interconnecting the patterned metal layers (330s and 330d); and
a stack of FET layers spaced apart by the IMD, each FET layer comprising a two- dimensional array of FET devices electrically connected with the metallization (FIG. 5A and 5B);
wherein each FET device includes:
source (302sd) and drain (302sd) regions;
a channel region (302) disposed between the source and drain regions;
a gate (314) arranged to selectively receive a bias voltage to selectively switch the FET between the first state and the second state;
a memory structure (306 and other layers) disposed between the gate and the channel region, and
Müller does not explicitly teach the memory structure including a first portion which is anti- ferroelectric and a second portion which is ferroelectric, the first and second portions being polarized in a first direction when the FET is in the first state; and at least one depolarization dielectric layer disposed proximate to the memory structure.
However, HEO teaches the memory structure including a first portion which is anti-ferroelectric (230) and a second portion which is ferroelectric (220) , the first and second portions being polarized in a first direction when the FET is in the first state and at least one depolarization dielectric layer (210) disposed proximate to the memory structure (Paragraph [0059]). Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use Müller’s FET to modify with teachings from HEO in order to obtain a FeRAM that has multiple logic states and spontaneous polarization of ferroelectrics may be maintained.
Claims 4-12, 14, 16-18 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Müller, in view of HEO and in further view of Müller et al. (US PGPub: 2022/0139937 A1), hereinafter Müller1.
Regarding claim 4, Müller or HEO (in view of Müller1) teaches the FET device of claim 2, wherein, when the FET is set to the second state, at least the first portion of the memory structure is, in an aggregate, unpolarized (Paragraph [0058] in Müller1).
Regarding claim 5, Müller or HEO (in view of Müller1) teaches the FET device of claim 4, wherein, when the FET is set to the second state, the at least one depolarization dielectric layer does not operate to polarize the first portion of the memory structure (Paragraph [0076]-[0079], [0088], [0054] in Müller1. Certainly polarization of these layers can be modified to have zero to any amount of polarization as well).
Regarding claim 6, Müller and HEO (in view of Müller1) teaches the FET device of claim 1, wherein the memory structure comprises a film of hafnium zirconium oxide (HZO), having a percentage of zirconium (Zr) in a range of between about 50% and about 80%, inclusive (Paragraph [0076]-[0079], [0088], [0054]) in Müller1. Certainly polarization of these layers can be modified to have zero to any amount of polarization as well).
Regarding claim 7, Müller or HEO (in view of Müller1) the FET device of claim 6, wherein the first portion comprises a tetragonal phase (T-phase) crystalline portion of the HZO film and the second portion comprises an orthorhombic phase (O-phase) crystalline portion of the HZO film (Paragraph [0076]-[0079], [0088] in Müller1. It is possible to have T-phase or other phase is possible as well).
Regarding claim 8, Müller or HEO (in view of Müller1) teaches the FET device of claim 7, wherein the T-phase crystalline portion is in a range of between about 2% and about 14% of the HZO film, inclusive; and the O- phase crystalline portion is in a range of between about 84% and about 88% of the HZO film, inclusive (Paragraph [0076]-[0079], [0088] in Müller1).
Regarding claim 9, Müller or HEO (in view of Müller1) teaches the FET device of claim 1, wherein the at least one depolarization dielectric layer comprises at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2) and zirconium oxide (ZrO2) (Paragraph [0054] in Müller1).
Regarding claim 10, Müller or HEO (in view of Müller1) teaches the FET device of claim 1, wherein the at least one depolarization dielectric layer has a thickness of about 2 nm or less (Paragraph [0054] in Müller1).
Regarding claim 11, Müller or HEO (in view of Müller1) teaches the FET device of claim 1, wherein the channel region comprises an oxide semiconductor layer (504 in FIG. 5D in Müller1).
Regarding claim 12, Müller or HEO (in view of Müller1) teaches the FET device of claim 1, wherein the at least one depolarization dielectric layer is disposed between the channel region and the memory structure (Paragraph [0076]-[0079], [0088] in Müller1, it is possible to have T-phase or other phase is possible as well).
Regarding claim 14, Müller or HEO (in view of Müller1) teach the FET device of claim 1, wherein the at least one depolarization dielectric layer includes two depolarization dielectric layers each disposed on opposite sides of the memory structure (Paragraph[0034] in Müller1).
Regarding claim 16, Müller and HEO (in view of Müller1) a three-dimensional memory array comprising: a three dimensional array of FET devices as set forth in claim 1;wherein the gates of the FET devices comprise electrically conductive word lines and the source regions comprise electrically conductive source lines and the drain regions comprise electrically conductive bit lines; wherein the electrically conductive source lines and the electrically conductive bit lines are perpendicular to the electrically conductive word lines (See FIG. 5A, 5B and 6 (also description) in Müller1).
Regarding claim 17, Müller teach a three-dimensional (3D) memory array comprising:
a plurality of electrically conductive word lines (WL1-3);
a plurality of electrically conductive bit lines (BL1-2) and electrically conductive source lines (SL1-2), the electrically conductive bit lines and electrically conductive source lines being perpendicular to the electrically conductive word lines (as in FIG. 5A); and
an array of memory cells, each memory cell including:
a channel region electrically connected between one of the electrically conductive source lines and one of the electrically conductive bit lines;
a memory film disposed between one of the electrically conductive word lines and the oxide semiconductor channel region.
Müller does not explicitly teach the memory structure including a first portion which is anti- ferroelectric and a second portion which is ferroelectric, the first and second portions being polarized in a first direction when the FET is in the first state; and at least one depolarization dielectric layer disposed proximate to the memory structure and wherein, when the memory cell is set to the first state, the depolarization dielectric layer creates an electric field which weakens a polarization of the ferroelectric domain of the memory film while maintaining a polarization of the anti- ferroelectric domain of the memory film and channel region comprises an oxide semiconductor layer
However, HEO teaches the memory structure including a first portion which is anti-ferroelectric (230) and a second portion which is ferroelectric (220) , the first and second portions being polarized in a first direction when the FET is in the first state and at least one depolarization dielectric layer (210) disposed proximate to the memory structure (Paragraph [0059]) and wherein, when the memory cell is set to the first state, the depolarization dielectric layer creates an electric field which weakens a polarization of the ferroelectric domain of the memory film while maintaining a polarization of the anti- ferroelectric domain of the memory film (Paragraph [0054]-[0058], [0068], [0084]-[0085]). Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use Müller’s FET to modify with teachings from HEO in order to obtain a FeRAM that has multiple logic states and spontaneous polarization of ferroelectrics may be maintained.
Müller or HEO does not explicitly teach channel region comprises an oxide semiconductor layer (504 in FIG. 5D in Müller1)
However, Müller1 teaches channel region comprises an oxide semiconductor layer (504 in FIG. 5D).
Hence, It would have been obvious to one of ordinary skill in the art at the time of the invention was made to use Müller and HEO’s modified FET to modify with teachings from Müller1 in order that a FeRAM with spontaneous polarization of ferroelectrics may be maintained.
Regarding claim 18, Müller and HEO (in view of Müller1) teach the 3D memory array of claim 17, wherein a magnitude of the electric field is proportional to a voltage drop (VDE) across the depolarization dielectric layer resulting from an application of the bias voltage divided by a thickness of the depolarization dielectric layer, and the thickness of the depolarization dielectric layer is established such that VDE falls between a first control voltage associated with the first anti-ferroelectric domain of the memory film and a second control voltage associated with the second ferroelectric domain, the first control voltage being greater than the second control voltage (Paragraph [0028]-[0031] of Müller1).
Regarding claim 21, Müller and HEO (in view of Müller1) teaches the three-dimensional memory array of claim 15, wherein: the channel region comprises an oxide semiconductor layer (channel region contains oxide semiconductor is known in the industry. complementary metal-oxide-semiconductor (CMOS) process flow in paragraph [0135] in Müller. The channel 111 may have a semiconductive property. For example, the channel 111 may include an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a two-dimensional (2D) material, a quantum dot, an organic semiconductor, and/or combinations thereof in addition to semiconductor materials such as Si, Ge, SiGe, and Group III-V semiconductors. For example, the oxide semiconductor may include InGaZnO in Paragraph [0050] of HEO); the memory structure comprises a film of hafnium zirconium oxide (HZO), having a percentage of zirconium (Zr) in a range of between about 50% and about 80%, inclusive; and the at least one depolarization dielectric layer has a thickness of about 2 nm or less and comprises at least one of aluminum oxide (Al203), hafnium oxide (HfO2) and zirconium oxide (ZrO2) (Paragraph [0076]-[0079], [0088], [0054]) in Müller1. Certainly polarization of these layers can be modified to have zero to any amount of polarization as well).
Regarding claim 22, Müller teach (in view if HEO) the FET device of claim 1, wherein the at least one depolarization dielectric layer (210) is disposed in contact with the memory structure (Paragraph [0059] in HEO).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHEIKH MARUF/Primary Examiner, Art Unit 2897