DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 05/11/2026.
Claims 1-22 are pending in this application.
Claims 15-22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Remarks
2. Applicant's arguments have been fully considered, but are moot in view of a new ground of rejection. See details below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1-2, and 5-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ajmera et al. (US 6,255,145)
Regarding claim 1, Ajmera discloses a semiconductor structure, comprising:
a bulk substrate 10 (see figs. 1-6; see also Annotated Drawing below) made of a semiconductor material and with an original semiconductor surface (attached to lower surface of oxide layer 12);
a first semiconductor island region (corresponding to one of region 22 in fig. 2, such region is surrounded by buried oxide layer 26 and trench isolation 30 in fig. 6) formed based on the bulk substrate 10 and under the original semiconductor surface (see col. 5, line 13-62);
a first STI region 30 (fig. 6) surrounding sidewalls of the first semiconductor island region;
a first buried insulator layer 26 which is formed and localized under the first semiconductor island region;
a second semiconductor island region (corresponding to the other of region 22 in fig. 2, such region is surrounded by buried oxide layer 26 and trench isolation 30 in fig. 6) formed based on the bulk substrate 10 and under the original semiconductor surface;
a second STI region 30 surrounding sidewalls of the second semiconductor island region; and
a second buried insulator layer 26 which is formed and localized under the second semiconductor island region;
wherein the first buried insulator layer is physically spaced apart from the second buried insulator layer.
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Regarding claim 2, Ajmera discloses the semiconductor structure according to claim 1, wherein:
a bottom surface of the first semiconductor island region is fully isolated from a rest portion of the bulk substrate 10 by the first buried insulator layer 26; and
a bottom surface of the second semiconductor island region is fully isolated from the rest portion of the bulk substrate 10 by the second buried insulator layer 26;
wherein the rest portion of the bulk substrate does not include the first semiconductor island region and the second semiconductor island region. See the Annotated Drawing above.
Regarding claim 5, Ajmera discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 26 laterally extends from an inner sidewall of the first STI region 30 to another inner sidewall of the first STI region (to adjacent island structure: even not shown in the drawing, but one of ordinary skills in the art would understand that a structure comprising a plurality of semiconductor islands, plurality of semiconductor body regions similar to what is shown in fig. 6 of Ajmera could and should be formed adjacent to each other to take the cost/time effective advantages etc., and this would involve only routine skills in the art).
Regarding claim 6, Ajmera discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 26 does not extend across all of the bulk substrate 10, and the second buried insulator layer 26 does not extend across all of the bulk substrate 10. See fig. 6.
Regarding claim 7, Ajmera discloses a semiconductor structure, comprising:
a bulk wafer 10 (see fig. 1-6, and the Annotated Drawing above) made of a semiconductor material and with an original semiconductor surface (attached to surface oxide layer 12);
a set of semiconductor island regions (corresponding to regions 22 in fig. 2, such regions are surrounded by buried oxide layers 26 and trench isolations 30 in fig. 6) selectively formed based on the bulk wafer 10 (see col. 5, line 13-62), wherein the set of semiconductor island regions are physically separate from each other and under the original semiconductor surface;
a set of shallow trench insulator (STI) regions 30 (fig. 6) corresponding to the set of semiconductor island regions respectively, wherein sidewalls of one semiconductor island region is surrounded by one corresponding STI region 30; and
a set of buried insulator layers 26 corresponding to the set of semiconductor island regions respectively, wherein the set of buried insulator layer 26 are under the original semiconductor surface and physically separate from each other, and a bottom surface of the one semiconductor island region is above one corresponding buried insulator layer 26;
wherein the bottom surface of the one semiconductor island (1st island & 2nd island) is fully isolated from a rest portion of the bulk wafer 10 by the one corresponding buried insulator layer 26 (1st & 2nd buried insulator layers), wherein the rest portion of the bulk wafer 10 does not include the set of semiconductor island regions.
Regarding claim 8, Ajmera discloses the semiconductor structure according to claim 7, wherein the one corresponding buried insulator layer 26 is surrounded by the one corresponding STI region 30. See the Annotated Drawing.
Regarding claim 9, Ajmera discloses the semiconductor structure according to claim 8, wherein the one corresponding buried insulator layer 26 laterally extends from an inner sidewall of the one corresponding STI region 30 to another inner sidewall of the one corresponding STI region (to adjacent island structure: even not shown in the drawing, but one of ordinary skills in the art would understand that a structure comprising a plurality of semiconductor islands, plurality of semiconductor body regions similar to what is shown in fig. 6 of Ajmera could and should be formed adjacent to each other to take the cost/time effective advantages etc., and this would involve only routine skills in the art).
Regarding claim 10, Ajmera discloses the semiconductor structure according to claim 9, wherein a lateral length of the one semiconductor island region is not greater than a lateral length of the one corresponding buried insulator layer. See fig. 6.
Regarding claim 11, Ajmera discloses the semiconductor structure according to claim 7, wherein the set of buried insulator layers 26 do not extend all over the bulk wafer. See fig. 6.
Regarding claim 12, Ajmera discloses a semiconductor structure, comprising:
a bulk substrate 10 (see figs. 1-6, and the Annotated Drawing above) made of a semiconductor material and with an original semiconductor surface;
a semiconductor island region (1st and/or 2nd islands) based on the bulk substrate 10 and under the original semiconductor surface;
a first STI region 30 surrounding the semiconductor island region;
a buried insulator layer 26 localized formed under the first semiconductor island region;
a semiconductor body region based on the bulk substrate 10, wherein the semiconductor island region is physically spaced apart from the semiconductor body region; and
a second STI region 30 surrounding the semiconductor body region;
wherein a bottom surface of the semiconductor island region is fully isolated from a rest portion of the bulk substrate 10 by the buried insulator layer 26, wherein the rest portion of the bulk substrate does not include the semiconductor island region and the semiconductor body region.
Regarding claim 13, Ajmera discloses the semiconductor structure according to claim 12, wherein the semiconductor body region is electrically coupled to the rest portion of the semiconductor body region. See the Annotated Drawing.
Regarding claim 14, Ajmera discloses the semiconductor structure according to claim 12, wherein a width, length or thickness of the buried insulator layer is adjustable. See col. 5, lines 13-52.
Claim Rejections - 35 U.S.C. § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ajmera et al. (US 6,255,143) in view of Tsuchiya (US 2009/0224321)
Regarding claims 3, and 4, Ajmera discloses the semiconductor structure according to claim 1, comprising all claimed limitations, as discussed above.
Ajmera is silent on wherein a width, length or thickness of the first buried insulator layer is different from that of the second buried insulator layer (claim 3), or wherein a width, length or thickness of the first semiconductor island region is different from that of the second semiconductor island region (claim 4).
Tsuchiya discloses a semiconductor structure, shown in fig. 26, comprising a first semiconductor island above a first buried oxide layer 4 (in region A1) and a second semiconductor island above a second buried oxide layer 4 (in region A2), wherein a width, length or thickness of the first buried insulator layer 4 is different from that of the second buried insulator layer 4, and/or or wherein a width, length or thickness of the first semiconductor island region is different from that of the second semiconductor island region.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Ajmera to have the first buried oxide layer having different length then that of the second buried oxide layer, and or to have the first semiconductor island region having different length then that of the second semiconductor island region.
It would have been obvious to one of ordinary skills in the art at the time the invention was made that this is just a matter of changing a size of a component or of the device, and it would involve only routine skills in the art. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Moreover, the instant specification contains no disclosure of either the critical nature of the claimed dimensions or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/Dao H Nguyen/
Primary Examiner, Art Unit 2818
July 5, 2026
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