DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 10/15/2025.
Claims 1-22 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, claims 1-14, is acknowledged.
Claims 15-22 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Acknowledges
2. Receipt is acknowledged of the following items from the Applicant.
Information Disclosure Statement (IDS) filed on 01/02/2024, and 09/19/2024. The references cited on the PTOL 1449 form have been considered.
Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609.
Specification
3. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objection
4. The claim is objected to for the following reason:
In claim 14, the limitation “the buried insulator layer” lacks an antecedent basis.
It is believed and presumed that claim 14 should depend upon claim 12 instead of upon claim 1 as instantly claimed. The search is performed based on such presumption.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-2, and 4-14 are rejected under 35 U.S.C. 102(a)(b) as being anticipated by Takizawa (US 7,847,352)
Regarding claim 1, Takizawa discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 11 (see fig. 15B) with an original semiconductor surface;
a first semiconductor island region (above buried oxide 31a and underneath gate electrode 33a/34a) formed based on the bulk semiconductor substrate 11;
a first STI region 28 surrounding sidewalls of the first semiconductor island region;
a first buried insulator layer 31a which is formed and localized under the first semiconductor island region;
a second semiconductor island region (above buried oxide 31b and underneath gate electrode 33b/34b) formed based on the bulk semiconductor substrate 11;
a second STI region 28 surrounding sidewalls of the second semiconductor island region; and
a second buried insulator layer 31b which is formed and localized under the second semiconductor island region;
wherein the first buried insulator layer 31a is physically spaced apart from the second buried insulator layer 31b.
Regarding claim 2, Takizawa discloses the semiconductor structure according to claim 1, wherein:
a bottom surface of the first semiconductor island region is fully isolated from a rest portion of the bulk semiconductor substrate 11 by the first buried insulator layer 31a; and
a bottom surface of the second semiconductor island region is fully isolated from the rest portion of the bulk semiconductor substrate 11 by the second buried insulator layer 31b;
wherein the rest portion of the bulk semiconductor substrate 11 does not include the first semiconductor island region and the second semiconductor island region. See fig. 15B.
Regarding claim 4, Takizawa discloses the semiconductor structure according to claim 1, wherein a width, length or thickness of the first semiconductor island region is different from that of the second semiconductor island region. See fig. 15B, and col. 11, lines 51-61; col. 12, lines 20-27.
Regarding claim 5, Takizawa discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 31a laterally extends from an inner sidewall of the first STI region 28 to another inner sidewall of the first STI region 28. See fig. 15B.
Regarding claim 6, Takizawa discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 31a does not extend across all of the bulk semiconductor substrate 11, and the second buried insulator layer 31b does not extend across all of the bulk semiconductor substrate 11. See fig. 11.
Regarding claim 7, Takizawa discloses a semiconductor structure, comprising:
a bulk semiconductor wafer 11 (Fig. 15B) with an original semiconductor surface;
a set of semiconductor island regions (above buried oxides 31a-31c and underneath gate electrode 33a/34a-33c-34c, respectively) selectively formed based on the bulk semiconductor wafer 11, wherein the set of semiconductor island regions are physically separate from each other;
a set of shallow trench insulator (STI) regions 28 corresponding to the set of semiconductor island regions respectively, wherein sidewalls of one semiconductor island region is surrounded by one corresponding STI region 28; and
a set of buried insulator layers 31a-31c corresponding to the set of semiconductor island regions respectively, wherein the set of buried insulator layer 31a-31c are under the original semiconductor surface and physically separate from each other, and a bottom surface of the one semiconductor island region is above one corresponding buried insulator layer;
wherein the bottom surface of the one semiconductor island is fully isolated from a rest portion of the bulk semiconductor wafer 11 by the one corresponding buried insulator layer, wherein the rest portion of the bulk semiconductor wafer 11 does not include the set of semiconductor island regions.
Regarding claim 8, Takizawa discloses the semiconductor structure according to claim 7, wherein the one corresponding buried insulator layer 31a/31c is surrounded by the one corresponding STI region 28. See Fig. 15B.
Regarding claim 9, Takizawa discloses the semiconductor structure according to claim 8, wherein the one corresponding buried insulator layer 31a-31c laterally extends from an inner sidewall of the one corresponding STI region 28 to another inner sidewall of the one corresponding STI region 28. See fig. 15B.
Regarding claim 10, Takizawa discloses the semiconductor structure according to claim 9, wherein a lateral length of the one semiconductor island region is not greater than a lateral length of the one corresponding buried insulator layer 31a-31c. See Fig. 15B.
Regarding claim 11, Takizawa discloses the semiconductor structure according to claim 7, wherein the set of buried insulator layers 31a-31c do not extend all over the bulk semiconductor wafer 11. See Fig. 15B.
Regarding claim 12, Takizawa discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 11 (Fig. 15B) with an original semiconductor surface;
a semiconductor island region (above buried oxide 31c and underneath gate electrode 33c/34c) based on the bulk semiconductor substrate 11;
a first STI region 28 surrounding the semiconductor island region;
a buried insulator layer 31c localized formed under the first semiconductor island region;
a semiconductor body region 14/17 based on the bulk semiconductor substrate 11, wherein the semiconductor island region is physically spaced apart from the semiconductor body region 14/17; and
a second STI region 28 surrounding the semiconductor body region 14/17;
wherein a bottom surface of the semiconductor island region is fully isolated from a rest portion of the bulk semiconductor substrate 11 by the buried insulator layer 31c, wherein the rest portion of the bulk semiconductor substrate 11 does not include the semiconductor island region and the semiconductor body region 14/17.
Regarding claim 13, Takizawa discloses the semiconductor structure according to claim 12, wherein the semiconductor body region 14/17 is electrically coupled to the rest portion of the semiconductor body region 11. See fig. 15B.
Regarding claim 14, Takizawa discloses the semiconductor structure according to claim 1, wherein a width, length or thickness of the buried insulator layer 31c is adjustable. See fig. 15B, and col. 9, line 36 – col. 10, line 45.
7. Claims 1-2, and 5-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Singh et al. (US 11,935,895)
Regarding claim 1, Singh discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 102 (see figs. 8-9) with an original semiconductor surface;
a first semiconductor island region 110 (on the left SOI region 103 shown in figs. 8-9) formed based on the bulk semiconductor substrate 102;
a first STI region 116 and 112 (on the left of dielectric spacer 112, see Figs. 8A/B) surrounding sidewalls of the first semiconductor island region 110;
a first buried insulator layer 108 which is formed and localized under the first semiconductor island region 110;
a second semiconductor island region 110 (on the right SOI region 103 shown in figs. 8-9) formed based on the bulk semiconductor substrate 106;
a second STI region 116 and 112 (on the right of dielectric spacer 112, see Figs. 8A/B) surrounding sidewalls of the second semiconductor island region 110; and
a second buried insulator layer 108 which is formed and localized under the second semiconductor island region 110;
wherein the first buried insulator layer 108 is physically spaced apart from the second buried insulator layer 108 (fig. 9).
Regarding claim 2, Singh discloses the semiconductor structure according to claim 1, wherein:
a bottom surface of the first semiconductor island region 110 (on the left SOI region 103 shown in figs. 8-9) is fully isolated from a rest portion of the bulk semiconductor substrate 106 by the first buried insulator layer 108; and
a bottom surface of the second semiconductor island region 110 (on the right SOI region 103 shown in figs. 8-9) is fully isolated from the rest portion of the bulk semiconductor substrate 106 by the second buried insulator layer 108;
wherein the rest portion of the bulk semiconductor substrate 106 does not include the first semiconductor island region 110 and the second semiconductor island region 110. See fig. 9.
Regarding claim 5, Singh discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 108 laterally extends from an inner sidewall of the first STI region 116/112 to another inner sidewall of the first STI region 116/112. See fig. 9.
Regarding claim 6, Singh discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 108 does not extend across all of the bulk semiconductor substrate 106, and the second buried insulator layer 108 does not extend across all of the bulk semiconductor substrate 106. See fig. 9.
Regarding claim 7, Singh discloses a semiconductor structure, comprising:
a bulk semiconductor wafer 102 (figs. 8-9) with an original semiconductor surface;
a set of semiconductor island regions 110 (on both sides of dielectric spacer 112, see Figs. 8A/B) selectively formed based on the bulk semiconductor wafer, wherein the set of semiconductor island regions 110 are physically separate from each other (fig. 9; see also col. 4, lines 17-23);
a set of shallow trench insulator (STI) regions 116 and 112 corresponding to the set of semiconductor island regions 110 respectively, wherein sidewalls of one semiconductor island region 110 is surrounded by one corresponding STI region 116 & 112; and
a set of buried insulator layers 108 corresponding to the set of semiconductor island regions 110 respectively, wherein the set of buried insulator layer 108 are under the original semiconductor surface and physically separate from each other, and a bottom surface of the one semiconductor island region 110 is above one corresponding buried insulator layer 108;
wherein the bottom surface of the one semiconductor island 110 is fully isolated from a rest portion of the bulk semiconductor wafer 102/106 by the one corresponding buried insulator layer 108, wherein the rest portion of the bulk semiconductor wafer 102/106 does not include the set of semiconductor island regions 110.
Regarding claim 8, Singh discloses the semiconductor structure according to claim 7, wherein the one corresponding buried insulator layer 108 is surrounded by the one corresponding STI region 116 &112. See fig. 9.
Regarding claim 9, Singh discloses the semiconductor structure according to claim 8, wherein the one corresponding buried insulator layer 108 laterally extends from an inner sidewall of the one corresponding STI region 116/112 to another inner sidewall of the one corresponding STI region 116/112. See fig. 9.
Regarding claim 10, Singh discloses the semiconductor structure according to claim 9, wherein a lateral length of the one semiconductor island region 110 is not greater than a lateral length of the one corresponding buried insulator layer 108. See fig. 9.
Regarding claim 11, Singh discloses the semiconductor structure according to claim 7, wherein the set of buried insulator layers 108 do not extend all over the bulk semiconductor wafer 106. See fig. 9.
Regarding claim 12, Singh discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 102/106 (see figs. 7-9) with an original semiconductor surface;
a semiconductor island region 110 (in region 103) based on the bulk semiconductor substrate 102/106;
a first STI region 116 surrounding the semiconductor island region;
a buried insulator layer 108 localized formed under the first semiconductor island region 110;
a semiconductor body region 114 based on the bulk semiconductor substrate 102/106, wherein the semiconductor island region 110 is physically spaced apart from the semiconductor body region 114; and
a second STI region 112 surrounding the semiconductor body region 114;
wherein a bottom surface of the semiconductor island region 110 is fully isolated from a rest portion of the bulk semiconductor substrate 106 by the buried insulator layer 108,
wherein the rest portion of the bulk semiconductor substrate 106 does not include the semiconductor island region 110 and the semiconductor body region 114.
Regarding claim 13, Singh discloses the semiconductor structure according to claim 12, wherein the semiconductor body region 114 is electrically coupled to the rest portion of the semiconductor body region 106. See fig. 9.
Regarding claim 14, Singh discloses the semiconductor structure according to claim 12, wherein a width, length or thickness of the buried insulator layer 108 is adjustable. See col. 2, line 31 – col. 3, line 16.
8. Claims 1-7, and 12 are rejected under 35 U.S.C. 102(a)(b) as being anticipated by Tsuchiya (2009/0224321)
Regarding claim 1, Tsuchiya discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 1 (see fig. 26) with an original semiconductor surface;
a first semiconductor island region 3 & 16 (in region A1) formed based on the bulk semiconductor substrate 1;
a first STI region 2 surrounding sidewalls of the first semiconductor island region;
a first buried insulator layer 4 (in region A1) which is formed and localized under the first semiconductor island region;
a second semiconductor island region 3 & 26 (in region A2) formed based on the bulk semiconductor substrate 1;
a second STI region 2 surrounding sidewalls of the second semiconductor island region; and
a second buried insulator layer 4 (in region A2) which is formed and localized under the second semiconductor island region;
wherein the first buried insulator layer 4 is physically spaced apart from the second buried insulator layer 4.
Regarding claim 2, Tsuchiya discloses the semiconductor structure according to claim 1, wherein:
a bottom surface of the first semiconductor island region 3 (in region A1) is fully isolated from a rest portion of the bulk semiconductor substrate 1 by the first buried insulator layer; and
a bottom surface of the second semiconductor island region 3 (in region A2) is fully isolated from the rest portion of the bulk semiconductor substrate 1 by the second buried insulator layer 4;
wherein the rest portion of the bulk semiconductor substrate 1 does not include the first semiconductor island region and the second semiconductor island region. See fig. 26.
Regarding claim 3, Tsuchiya discloses the semiconductor structure according to claim 1, wherein a width, length or thickness of the first buried insulator layer 4 is different from that of the second buried insulator layer 4. See fig. 26.
Regarding claim 4, Tsuchiya discloses the semiconductor structure according to claim 1, wherein a width, length or thickness of the first semiconductor island region 3 & 16 is different from that of the second semiconductor island region 3 & 26. See fig. 26.
Regarding claim 5, Tsuchiya discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 4 laterally extends from an inner sidewall of the first STI region 2 to another inner sidewall of the first STI region 2. See fig. 26.
Regarding claim 6, Tsuchiya discloses the semiconductor structure according to claim 1, wherein the first buried insulator layer 4 does not extend across all of the bulk semiconductor substrate 1, and the second buried insulator layer 4 does not extend across all of the bulk semiconductor substrate 1. See fig. 26.
Regarding claim 7, Tsuchiya discloses a semiconductor structure, comprising:
a bulk semiconductor wafer 1 (fig. 26) with an original semiconductor surface;
a set of semiconductor island regions 3 &16, 4 & 16 selectively formed based on the bulk semiconductor wafer 1, wherein the set of semiconductor island regions are physically separate from each other;
a set of shallow trench insulator (STI) regions 2 corresponding to the set of semiconductor island regions respectively, wherein sidewalls of one semiconductor island region is surrounded by one corresponding STI region 2; and
a set of buried insulator layers 4 corresponding to the set of semiconductor island regions respectively, wherein the set of buried insulator layer 4 are under the original semiconductor surface and physically separate from each other, and a bottom surface of the one semiconductor island region is above one corresponding buried insulator layer;
wherein the bottom surface of the one semiconductor island 3 & 16, 4 & 16 is fully isolated from a rest portion of the bulk semiconductor wafer 1 by the one corresponding buried insulator layer 4, wherein the rest portion of the bulk semiconductor wafer 1 does not include the set of semiconductor island regions.
Regarding claim 12, Tsuchiya discloses a semiconductor structure, comprising:
a bulk semiconductor substrate 1 (fig. 26) with an original semiconductor surface;
a semiconductor island region 3 & 16 (in region A1) based on the bulk semiconductor substrate 1;
a first STI region 2 surrounding the semiconductor island region 3 & 16;
a buried insulator layer 4 localized formed under the first semiconductor island region 3 & 16;
a semiconductor body region 3 (in region A2) based on the bulk semiconductor substrate 1, wherein the semiconductor island region 3 & 16 (in region A1) is physically spaced apart from the semiconductor body region 3 (in region A2); and
a second STI region 2 surrounding the semiconductor body region;
wherein a bottom surface of the semiconductor island region is fully isolated from a rest portion of the bulk semiconductor substrate 1 by the buried insulator layer 4, wherein the rest portion of the bulk semiconductor substrate 1 does not include the semiconductor island region 3 & 16 and the semiconductor body region 3.
Conclusion
9. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 November 29, 2025