DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 07 Jul 2026 for application number 18/203,654. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-17 are presented for examination. Elected claims 10-17 are examined below; non-elected claims 1-9 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because of new grounds of rejection necessitated by amendment; see the Rejection below for prior art mappings and explanations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. [hereinafter as Li] (US 2016/0133524 A1) in view of Lin et al. [hereinafter as Lin] (US 2020/0135851 A1).
In reference to claim 10, Li teaches A semiconductor device, comprising:
a substrate [substrate 12; Fig. 23, para 0046] comprising a first active region [active region 22; Fig. 23, para 0048];
a shallow trench isolation (STI) [isolation regions 20; Fig. 20, para 0043] around the substrate [12];
a first divot [void 136; Figs. 22-23, para 0046] adjacent to one side of the first active region [22];
a second divot [136 on other side of 22] adjacent to another side of the first active region [22]; and
a gate structure [gate oxide layer 144; Fig. 23, para 0048] on the first active region [22].
However, Li does not explicitly teach wherein the STI directly contacts both opposite sidewalls of the first divot.
Lin teaches wherein the STI [isolation structure 104; Fig. 1A, para 0024] directly contacts both opposite sidewalls [104 contacts both sidewalls of 108] of the first divot [divot 108; Fig. 1A, para 0024].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Li and Lin before the effective filing date of the claimed invention, to include the divots as disclosed by Lin into the semiconductor device of Li in order to obtain a semiconductor device with STIs contacting both sidewalls of a divot.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with STIs contacting both sidewalls of a divot to provide the predictable result of optimizing local mechanical stress distribution and improving drive current performance.
In reference to claim 15, Li and Lin teach the inventio of claim 10.
Li teaches The semiconductor device of claim 10, wherein the first active region [22] is extending along a first direction [22 extends along horizontal direction] on the substrate [12].
In reference to claim 16, Li and Lin teach the inventio of claim 15.
Li teaches The semiconductor device of claim 15, wherein the first divot [136] is extending along the first direction [136 is positioned in the horizontal direction on one side of 22] adjacent to one side of the first active region [22] in a top view.
In reference to claim 17, Li and Lin teach the inventio of claim 15.
Li teaches The semiconductor device of claim 15, wherein the second divot [136 on other side of 22] is extending along the first direction [136 are positioned on either side of 22] adjacent to another side of the first active region [22] in a top view.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Lin further in view of Huang et al. [hereinafter as Huang] (US 2023/0246030 A1).
In reference to claim 11, Li and Lin teach the invention of claim 10.
Li teaches The semiconductor device of claim 10, wherein the substrate comprises a medium-voltage (MV) region [medium voltage device area 16; Fig. 20, para 0043] and a low-voltage (LV) region [low voltage device area 14; Fig. 20, para 0043], the semiconductor device comprising:
the first active region [22] on the MV region [16] and a second active region [22 in 14] on the LV region [14];
the shallow trench isolation (STI) [isolation regions 20; Fig. 20, para 0043] between the first active region [22] and the second active region [22 in 14];
However, Li and Lin do not explicitly teach:
a liner in the first divot and the second divot; and
a dielectric layer on the liner and the substrate.
Li and Huang teach:
a liner [masking layer 706 of Huang; Fig. 7, para 0022] in the first divot [136 of Li] and the second divot [136 on other side of 22 of Li]; and
a dielectric layer [hard mask layer 714 of Huang; Fig. 7, para 0022] on the liner [706 of Huang] and the substrate [12 of Li].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Li, Lin, and Huang before the effective filing date of the claimed invention, to include the liner and dielectric layer as disclosed by Huang into the semiconductor device of Li and Lin in order to obtain a semiconductor device with multiple regions of varying voltage with a liner and dielectric layer.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with multiple regions of varying voltage with a liner and dielectric layer to provide the predictable result of providing mechanical support, electrical insulation, ensuring reliability, thereby optimizing device performance.
In reference to claim 12, Li, Lin, and Huang teach the invention of claim 11.
Huang teaches The semiconductor device of claim 11, wherein the liner [706] and the dielectric layer [714] comprise different materials [para 0022 discloses that 706 may be silicon nitride and 714 may be silicon dioxide].
In reference to claim 13, Li, Lin, and Huang teach the invention of claim 11.
Huang teaches The semiconductor device of claim 11, wherein the liner [706] comprises silicon nitride [para 0022 discloses that 706 may be silicon nitride].
In reference to claim 14, Li, Lin, and Huang teach the invention of claim 11.
Huang teaches The semiconductor device of claim 11, wherein the dielectric layer [714] comprises silicon oxide [para 0022 discloses that 714 may be silicon dioxide, a type of silicon oxide].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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