Prosecution Insights
Last updated: July 15, 2026
Application No. 18/203,654

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Final Rejection §102§103
Filed
May 31, 2023
Priority
Apr 27, 2023 — TW 112115663
Examiner
CHUNG, ANDREW
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Microelectronics Corp.
OA Round
2 (Final)
55%
Grant Probability
Moderate
3-4
OA Rounds
8m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 55% of resolved cases
55%
Career Allowance Rate
177 granted / 323 resolved
-13.2% vs TC avg
Strong +32% interview lift
Without
With
+32.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
23 currently pending
Career history
353
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
93.8%
+53.8% vs TC avg
§102
4.5%
-35.5% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 323 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is sent in response to Applicant’s Communication received 06 Jan 2026 for application number 18/203,654. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims. Claims 1-17 are presented for examination. Elected claims 10-17 are examined below; non-elected claims 1-9 have been withdrawn. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 16 Mar 2026 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Response to Arguments Regarding claim 10, Applicant contends that the prior art does not teach, “wherein the STI is adjacent to two sides of the first divot”; Examiner respectfully disagrees. Firstly, the language, “is adjacent to two sides of the first divot” can be interpreted broadly. The current claim language does not provide further description as to what constitutes, “adjacent,” beyond the common meaning of the term. As such, Li teaches, wherein the STI [20] is adjacent to two sides of the first divot [136]. As can be seen in Fig. 22 of Li, the STI 20 is adjacent to two sides of the first divot 136, as portions of STI 20 are “next to,” i.e. adjacent, the sides of first divot 136. As express before, as no further description of “adjacent” is presented, Li reasonably teaches, “wherein the STI is adjacent to two sides of the first divot.” Dependent claims 15-17 are rejected for these reasons and for reasons as expressed in the rejection below. Dependent claims 11-14 are rejected for these reasons and for reasons as expressed in the rejection below. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 10 and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. [hereinafter as Li] (US 2016/0133524 A1). In reference to claim 10, Li teaches A semiconductor device, comprising: a substrate [substrate 12; Fig. 23, para 0046] comprising a first active region [active region 22; Fig. 23, para 0048]; a shallow trench isolation (STI) [isolation regions 20; Fig. 20, para 0043] around the substrate [12]; a first divot [void 136; Figs. 22-23, para 0046] adjacent to one side of the first active region [22], wherein the STI [20] is adjacent to two sides of the first divot [136]; a second divot [136 on other side of 22] adjacent to another side of the first active region [22]; and a gate structure [gate oxide layer 144; Fig. 23, para 0048] on the first active region [22]. In reference to claim 15, Li teaches The semiconductor device of claim 10, wherein the first active region [22] is extending along a first direction [22 extends along horizontal direction] on the substrate [12]. In reference to claim 16, Li teaches The semiconductor device of claim 15, wherein the first divot [136] is extending along the first direction [136 is positioned in the horizontal direction on one side of 22] adjacent to one side of the first active region [22] in a top view. In reference to claim 17, Li teaches The semiconductor device of claim 15, wherein the second divot [136 on other side of 22] is extending along the first direction [136 are positioned on either side of 22] adjacent to another side of the first active region [22] in a top view. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li in view of Huang et al. [hereinafter as Huang] (US 2023/0246030 A1). In reference to claim 11, Li teaches the invention of claim 10. Li teaches The semiconductor device of claim 10, wherein the substrate comprises a medium-voltage (MV) region [medium voltage device area 16; Fig. 20, para 0043] and a low-voltage (LV) region [low voltage device area 14; Fig. 20, para 0043], the semiconductor device comprising: the first active region [22] on the MV region [16] and a second active region [22 in 14] on the LV region [14]; the shallow trench isolation (STI) [isolation regions 20; Fig. 20, para 0043] between the first active region [22] and the second active region [22 in 14]; However, Li does not explicitly teach: a liner in the first divot and the second divot; and a dielectric layer on the liner and the substrate. Li and Huang teach: a liner [masking layer 706 of Huang; Fig. 7, para 0022] in the first divot [136 of Li] and the second divot [136 on other side of 22 of Li]; and a dielectric layer [hard mask layer 714 of Huang; Fig. 7, para 0022] on the liner [706 of Huang] and the substrate [12 of Li]. It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Li and Huang before the effective filing date of the claimed invention, to include the liner and dielectric layer as disclosed by Huang into the semiconductor device of Li in order to obtain a semiconductor device with multiple regions of varying voltage with a liner and dielectric layer. One of ordinary skill in the art would be motivated to obtain a semiconductor device with multiple regions of varying voltage with a liner and dielectric layer to provide the predictable result of providing mechanical support, electrical insulation, ensuring reliability, thereby optimizing device performance. In reference to claim 12, Li and Huang teach the invention of claim 11. Huang teaches The semiconductor device of claim 11, wherein the liner [706] and the dielectric layer [714] comprise different materials [para 0022 discloses that 706 may be silicon nitride and 714 may be silicon dioxide]. In reference to claim 13, Li and Huang teach the invention of claim 11. Huang teaches The semiconductor device of claim 11, wherein the liner [706] comprises silicon nitride [para 0022 discloses that 706 may be silicon nitride]. In reference to claim 14, Li and Huang teach the invention of claim 11. Huang teaches The semiconductor device of claim 11, wherein the dielectric layer [714] comprises silicon oxide [para 0022 discloses that 714 may be silicon dioxide, a type of silicon oxide]. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANDREW CHUNG/ Examiner, Art Unit 2898 /JESSICA S MANNO/SPE, Art Unit 2898
Read full office action

Prosecution Timeline

May 31, 2023
Application Filed
Nov 26, 2025
Non-Final Rejection mailed — §102, §103
Jan 06, 2026
Response Filed
Apr 24, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
55%
Grant Probability
87%
With Interview (+32.0%)
3y 9m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 323 resolved cases by this examiner. Grant probability derived from career allowance rate.

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