Prosecution Insights
Last updated: April 19, 2026
Application No. 18/203,655

Barrier Layers for Interconnects in Bonded Wafers

Final Rejection §112
Filed
May 31, 2023
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
2 (Final)
70%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
91%
With Interview

Examiner Intelligence

Grants 70% — above average
70%
Career Allow Rate
478 granted / 678 resolved
+2.5% vs TC avg
Strong +20% interview lift
Without
With
+20.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
36 currently pending
Career history
714
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.0%
+7.0% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
22.9%
-17.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 678 resolved cases

Office Action

§112
DETAILED ACTION This office action is in response to the amendment filed 11/20/2025. Currently, claims 1-3, 5, 7-11, 13 and 15-16 are pending. Claims 4, 6, 12 and 14 have been canceled. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5, 7, 13 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 5 and 13 recite the limitation “a width of the second barrier layer is less than a width of the first barrier layer”. It is not clear what is meant by “width of the … barrier layer” in the context of the disclosure. For purposes of examination, it is presumed that the width is referring to the total width of the barrier layer and the metal layer associated therewith, as shown in FIG. 2. Claims 7 and 15 recite the limitation “a bottom surface of the second barrier layer is lower than the interface between the inter-metal dielectric layer and the interlayer dielectric layer”. This language is confusing because it appears to use contradicting orientations to describe certain features. The term “bottom surface” is used to describe the surface of the top wafer on which the dielectric layer resides (claims 1 and 9), and also to describe the surface of the second barrier layer relative to the interface between the inter-metal dielectric layer and the interlayer dielectric, as recited in claims 7 and 15. Referencing FIG. 1 and 2, the bottom surface of the top wafer would be the surface closest to the top of the page (i.e. contacting dielectric 66), while the bottom surface of the second barrier layer would be the surface closest to the bottom of the page. In other words, “bottom surface” is an orientationally-dependent term, but that orientation does not appear to be consistent, leading to confusion. This further confuses what is meant by “lower”, as there does not appear to be a consistent orientation being referenced. Allowable Subject Matter Claims 1-3, 8-11 and 16 are allowed. The following is an examiner’s statement of reasons for allowance: The amendments overcome the previous prior art rejections as argued by Applicant in the 11/20/2025 remarks. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Response to Arguments As indicated above, Applicant’s arguments with respect to the prior art rejections are persuasive. With respect to the arguments addressing rejections under 35 U.S.C. 112, while the cancellation of claims 4, 6, 12 and 14 renders those rejections moot, there are still outstanding rejections of claims 5, 7, 13 and 15 that were not addressed in the arguments. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

May 31, 2023
Application Filed
Sep 24, 2025
Non-Final Rejection — §112
Nov 20, 2025
Response Filed
Mar 19, 2026
Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604725
INTERLEVEL DIELECTRIC STRUCTURE IN SEMICONDUCTOR DEVICE
2y 5m to grant Granted Apr 14, 2026
Patent 12598977
FILL OF VIAS IN SINGLE AND DUAL DAMASCENE STRUCTURES USING SELF-ASSEMBLED MONOLAYER
2y 5m to grant Granted Apr 07, 2026
Patent 12575310
DISPLAY APPARATUS HAVING A REPAIR WIRING
2y 5m to grant Granted Mar 10, 2026
Patent 12568815
WIRINGS FOR SEMICONDUCTOR DEVICE ARRANGED AT DIFFERENT INTERVALS AND HAVING DIFFERENT WIDTHS
2y 5m to grant Granted Mar 03, 2026
Patent 12564025
Interconnect with Redeposited Metal Capping and Method Forming Same
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
70%
Grant Probability
91%
With Interview (+20.5%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 678 resolved cases by this examiner. Grant probability derived from career allow rate.

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