DETAILED ACTION
This correspondence is in response to the communications received April 22, 2026. Claims 1-28 are pending.
Response to Arguments
In response to the newly amended claim 1 and the previous 103 rejection in view of Hamaguchi, it appears that the amendment does overcome Fig. 1 of Hamaguchi for the reason that the heavily doped region 27 is under the lightly doped region 21. Just to note however it is shown in the Hamaguchi reference Fig. 1, that the lightly doped region 21 is laterally adjacent to the channel portion of the semiconductor substrate 28. In response to the arguments against the rejections of claims 5, 6 and 11, with regard to the newly amended claim language of claim 1, it is noted that this feature is now fully rejected in this response to the newly amended claim language of claim 1, see rejection below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
In response to the now allowable claims 19 and 22, claims 20, 26 and 27, which had been previously withdrawn from consideration as a result of a restriction requirement, are hereby rejoined and fully examined for patentability under 37 CFR 1.104.
Because all claims previously withdrawn from consideration under 37 CFR 1.142 have been rejoined, the restriction requirement as set forth in the Office action mailed on July 31, 2025 is hereby withdrawn. In view of the withdrawal of the restriction requirement as to the rejoined inventions, applicant(s) are advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application. Once the restriction requirement is withdrawn, the provisions of 35 U.S.C. 121 are no longer applicable. See In re Ziegler, 443 F.2d 1211, 1215, 170 USPQ 129, 131-32 (CCPA 1971). See also MPEP § 804.01.
Claim Objections
The amendment to claim 26 has overcome the objection, which is hereby withdrawn.
Claim Rejections - 35 USC § 112
Applicant’s amendment to claim 22 and explanation included overcome the previous 112b rejection, which is hereby withdrawn.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 28 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The newly included claim 28 recitation of, “a top surface of the vertically extended isolation region is higher than the semiconductor surface”, lacks support in the specification and the drawings, and is hereby considered to be “new matter”. Regarding claim 28, it is noted that the prior art of Hamaguchi discloses wherein the localized isolation region includes a vertically extended isolation region (Hamaguchi’s vertical extension portion of 17), two opposite sides of the vertically extended isolation contact the heavily doped semiconductor region of the first conductive region (inner/left most surface of the vertical portions of 17 contact 27 of left most 27) and the heavily doped semiconductor region of the second conductive region (inner/right most surface of the vertical portions of 17 contact 27 of tight most 27).
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Figs. 1A, 9A, 9B, 10C, a DRAM circuit, comprising:
a semiconductor substrate (“p-type silicon substrate”) with a semiconductor surface (upper surface thereof where the transistor is formed);
an array core circuit (172, Fig. 1A) with a sense amplifier circuit and a plurality of DRAM cells electrically coupled to the sense amplifier circuit (¶ 0003); and
a peripheral circuit (171, Fig. 1A) electrically coupled to the array core circuit, wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET
structure (paragraphs 0002, 0003), the complementary MOSFET structure comprising:
a planar P type MOSFET (transistor in the n-well) comprising a first conductive region (this is understood to mean the source/drain regions of this particular transistor);
a planar N type MOSFET (transistor in p-substrate) comprising a second conductive region (this is understood to mean the source/drain regions of this particular transistor);
a localized isolation region (combination of features of STI, oxide 411, 412 and nitride 42) between the planar P type MOSFET and the planar N type MOSFET (formed between the two transistors),
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wherein the localized isolation region includes a horizontally extended isolation region below the semiconductor surface (411, 412 and 42 extend horizontally ‘under’ the semiconductor source drain regions, see Fig. 10C), and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region (It appears that the “conductive regions” are the source drain regions of the transistors, 431, 432),
wherein each of the first conductive region and the second conductive region includes a lightly doped semiconductor region (430, ¶ 0067) and a heavily doped semiconductor region (431, 432, ¶ 0067),
the lightly doped semiconductor region (430) laterally extends from an edge of the semiconductor substrate (this limitation is understood to mean that the semiconductor substrate has a portion that is vertically level with the 430, which can be seen in Fig. 10C), and
the heavily doped semiconductor region laterally extends from a lateral side of the lightly doped semiconductor region (this limitation is understood to mean that the heavily doped semiconductor region 431, 432 is vertically level with and extending from the lightly doped semiconductor region 430, which can be seen in Fig. 10C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara et al. (US 2021/0167041) in view of Tanzawa (US 8,952,482) in view of Mori et al. (US 2009/0040850) in view of Hamaguchi (US 2006/0131657) in view of Chen et al. (US 11,562,923) in view of Liang et al. (US 6,071,783).
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Regarding claim 1, the prior art of Yoshihara discloses in Fig. 3, a DRAM circuit (DRAM will be addressed by the combination rejection in view of Tanzawa below), comprising:
a semiconductor (The term “semiconductor” is used to describe the device in this application, in the title and throughout the description of active layers such as “semiconductor pillar”, ¶ 0076) substrate (“memory chip 100”, ¶ 0059) with a semiconductor surface (surface of chip 100, where the following aspects are disposed upon);
an array core circuit (“core circuit 110”, ¶ 0059) with a sense amplifier circuit (“SENSE AMPLIFIER MODULE” 109_0, 109_1, hereinafter referred to as ‘SAC’) and a plurality of memory cells (plural 101_0, 101_1, “MEMORY CELL ARRAY”, hereinafter referred to as ‘MCA’) electrically coupled (electrically coupled through the arrow, symbolically representing electrical connection, hereinafter referred to as ‘EC’) to the sense amplifier circuit (SAC and MCA are connected electrically through the EC); and
a peripheral circuit (“peripheral circuit 120”, ¶ 0060) electrically coupled to the array core circuit (110 electrically connects to 112 through several electrical connections, symbolically represented by the arrows connecting 120 to the elements within 110).
First, Yoshihara does not specify, that the memory cells are specifically “a plurality of DRAM cells”.
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Tanzawa discloses in Fig. 3 and col. 4, line 66 to col. 5, line 5, “The memory array region 305 may comprise various types of volatile or non-volatile memory cells including flash memory, conductive-bridging random access memory (CBRAM), resistive RAM (RRAM), phase change memory (PCM), static RAM (SRAM), dynamic RAM (DRAM), or various other types and combinations of types of memory devices.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the memory cells are specifically “a plurality of DRAM cells”, as disclosed by Tanzawa in the system of Yoshihara, for the purpose of utilizing high density computational temporary holding memory cells. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Yoshihara does not specify, “wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure”.
Mori discloses a sense amplifier composed of CMOS devices, ¶ 0128, “The sense amplifier SA is formed by a pair of CMOS inverters having inputs and outputs coupled to each other. The inputs of each CMOS inverter (gates of the transistors) are coupled to the bit line BL (or /BL). Each CMOS inverter is formed by an nMOS transistor and a pMOS transistor arranged in the horizontal direction of the diagram.”
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein either the sense amplifier circuit or the peripheral circuit has a complementary MOSFET structure”, as disclosed by Mori in the system of Yoshihara, for the purpose of utilizing a configuration which can reduce power requirements. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Third, Yoshihara does not disclose,
“the MOSFET structure comprising:
a planar P type MOSFET comprising a first conductive region;
a planar N type MOSFET comprising a second conductive region;
a localized isolation region between the planar P type MOSFET and the planar N type MOSFET, wherein the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region,
wherein each of the first conductive region and the second conductive region includes a lightly doped semiconductor region and a heavily doped semiconductor region,
the lightly doped semiconductor region laterally extends from an edge of the semiconductor substrate”.
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Hamaguchi discloses in Figs. 1 and 2A-2I, the MOSFET structure comprising:
a planar P type MOSFET (“pMOS element region 44”, ¶ 0029) comprising a first conductive region (source/drain region 27 in 44, ¶ 0030, hereinafter referred to as ‘FCR’);
a planar N type MOSFET (“nMOS element region 43”, ¶ 0029) comprising a second conductive region (source/drain region 27 in 43, ¶ 0030, hereinafter referred to as ‘SCR’);
a localized isolation region between the planar P type MOSFET and the planar N type MOSFET (combination of features of STI 11, ¶ 0029 and “insulation film (embedded insulation film) 17”, ¶ 0030, hereinafter referred to as ‘LIR’),
wherein the localized isolation region includes a horizontally extended isolation region below the semiconductor surface (17 extend horizontally under the surface of 40’s regions 41 and 42, which extend to the top of plane at top surface of 11), and the horizontally extended isolation region (17) contacts to a bottom side of the first conductive region and a bottom side of the second conductive region (17 contact the under side of both of source/drain regions 17 of 43 and 44),
wherein each of the first conductive region (FCR) and the second conductive region (SCR) includes a lightly doped semiconductor region (“a shallow extension region 21 of a low impurity concentration is formed.”, ¶ 0043) and a heavily doped semiconductor region (“source/drain region 27 of a high impurity concentration”, ¶ 0046),
the lightly doped semiconductor region laterally extends from an edge of the semiconductor substrate (21 extends laterally from the top most portion of the channel region 18 of the semiconductor substrate “a p-well 41 and an n-well 42 are formed on the surface region of the Si semiconductor substrate 40.”, ¶ 0049).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“the MOSFET structure comprising:
a planar P type MOSFET comprising a first conductive region;
a planar N type MOSFET comprising a second conductive region;
a localized isolation region between the planar P type MOSFET and the planar N type MOSFET, wherein the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region,
wherein each of the first conductive region and the second conductive region includes a lightly doped semiconductor region and a heavily doped semiconductor region,
the lightly doped semiconductor region laterally extends from an edge of the semiconductor substrate”, as disclosed by Hamaguchi in the system of Yoshihara, for the purpose of providing further electrical isolation between neighboring active devices, to further decrease cross talk and unwanted electrical influence from neighboring devices. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Fourth, Hamaguchi does not specify that the source/drain regions are specifically, “conductive regions.”
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Chen discloses in Figs. 7-9, wherein “conductive regions 704 are at least one of a source region or a drain region”, col. 8, lines 26-27.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of the source/drain regions are specifically, “conductive regions.”, as disclosed by Chen in the system of Yoshihara, for the purpose of providing the necessary features of a MOSFET transistor to contribute to the overall transistor device’s function as a switching device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Fifth, Yoshihara does not disclose, “the heavily doped semiconductor region laterally extends from a lateral side of the lightly doped semiconductor region.”
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Liang discloses in Fig. 8, the heavily doped semiconductor region (“heavily doped source/drain region 12”, col. 4, line 65) laterally extends from a lateral side of the lightly doped semiconductor region (“lightly doped source drain segment 6b”, col. 4, line 67, where 12 has a portion that extends laterally from 6b, 6c).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “the heavily doped semiconductor region laterally extends from a lateral side of the lightly doped semiconductor region”, as disclosed by Liang in the system of Yoshihara, for the purpose of providing the necessary features of a MOSFET transistor to contribute to the overall transistor device’s function as a switching device by at least reducing device degradation due to hot electron effects. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 1, and Hamaguchi discloses in Figs. 1 and 2A-2I (already presented in the combination rejection of claim 1), wherein the complementary MOSFET structure further comprises a first concave (¶ 0038, “trenches” in Fig. 2B, then still present in Fig. 2C, where 17 is deposited and patterned) formed below the semiconductor surface (noted trench delves into the substrate below the upper plane of the semiconductor substrate which initially shared the upper surface plane of the STI 11), and the first concave accommodates the first conductive region (27 is accommodated in the earlier formed trench, see Fig. 1 and 2I).
Regarding claim 3, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 2, wherein the first conductive region comprises an undoped semiconductor region and/or a lightly doped semiconductor region (Hamaguchi discloses in Fig. 1, where 21 is a lightly doped region, ¶ 0043), and the first conductive region (27) is independent from the semiconductor substrate (27 is independent or separate from the substrate 40/42).
Regarding claim 4, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 3, wherein the undoped semiconductor region or the lightly doped semiconductor region (Hamaguchi discloses in Fig. 1, where 21 is a lightly doped region, ¶ 0043) abuts against a channel region (Hamaguchi’s “channel region 28”, ¶ 0030) of the planar P type MOSFET (region 21 abuts the channel region 28, as can be seen in Fig. 1, for pMOS device in region 44).
Regarding claim 7, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 1, and Hamaguchi discloses in Fig. 1, wherein the complementary MOSFET structure further comprises a first concave (trench 45, ¶ 0038) formed below the semiconductor surface (45 below top surface at channel and STI upper surface level), the first concave (45) accommodates a first portion of the horizontally extended isolation region (45 accommodates 17).
Regarding claim 8, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 7, and Hamaguchi discloses in Fig. 1, wherein the planar P type MOSFET (transistor in region 44) further comprises a gate region (13a, ¶ 0031) over the semiconductor surface (over channel 28 of 40), and an edge of the gate region is aligned or substantially aligned with an edge of the first conductive region (lower edge of 13a and upper edges of 27 are aligned. It is noted that the LDD 21 is an overlay on 27, so we see 21 over 27 in Fig. 1, but 27 doping starts at surface and then extends down to lowest boundary.).
Regarding claim 9, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 7, and Hamaguchi discloses in Fig. 1, wherein the planar P type MOSFET (transistor in region 44) further comprises a gate region (13a, ¶ 0031), and all of the first portion of the horizontally extended isolation region is not directly underneath the gate structure (17 not under 13a).
Regarding claim 10, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 7, and Hamaguchi discloses in Fig. 1, wherein the planar P type MOSFET (transistor in region 44) further comprises a gate region (13a, ¶ 0031), and less than 5% of the first portion of the horizontally extended isolation region is directly underneath the gate structure (17 not under 13a).
Regarding claim 13, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 1, and Hamaguchi discloses in Fig. 1, wherein the horizontally extended isolation region includes a first horizontally extended isolation region (17 in transistor region 44) and a second horizontally extended isolation region (17 in transistor region 43), the bottom side of the first conductive region is shielded from the semiconductor substrate by the first horizontally extended isolation region (bottom of 27 is shielded from 40/42 by 17 in the transistor region 44), and the bottom side of the second conductive region is shielded from the semiconductor substrate by the second horizontally extended isolation region (bottom of 27 is shielded from 40/42 by 17 in the transistor region 43).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara et al. (US 2021/0167041) in view of Tanzawa (US 8,952,482) in view of Mori et al. (US 2009/0040850) in view of Hamaguchi (US 2006/0131657) in view of Chen et al. (US 11,562,923) in view of Liang et al. (US 6,071,783) in view of Wristers et al. (US 6,707,106).
Regarding claim 5, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 3, the first conductive region further comprising a heavily doped semiconductor region (Hamaguchi’s Fig. 1, shows heavy doped regions P+ 27), wherein the heavily doped semiconductor region is positioned in the first concave (in trench 45 with 17, see Fig. 2B and Fig. 1).
Then, Yoshihara et al. do not disclose, “the lightly doped semiconductor region and the heavily doped semiconductor region are formed with same lattice structure.”
Wristers discloses in Figs. 4A-4C and in, “the silicon lattice strains to match the lattice spacing of the SiGe layer 60. Lightly doped source/drain extensions 64 are formed in the strained silicon layer 62.”, col. 5, lines 55-61. Both of the source /drain regions 70 (col. 5, line 65) and the lightly doped regions 64 (col. 5, lines 58-61) are formed in lattice matched layers 60 and 62. So by doping the source drain regions and lightly doped regions into lattice matched layers, the source / drain regions and the lightly doped regions then share the same lattice structure.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “the lightly doped semiconductor region and the heavily doped semiconductor region are formed with same lattice structure.”, as disclosed by Wristers in the system of Yoshihara, for the purpose improving performance characteristics of the transistor device. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 5, however Yoshihara does not disclose, “wherein the first conductive region further comprising a metal region, the metal region is positioned in the first concave and abuts against the heavily doped semiconductor region.”
Wristers discloses in Fig. 4C, wherein the first conductive region (70) further comprising a metal region (72, “s shown in FIG. 4C, conductive silicide layers 72 can be formed on the gate structure 96 and source/drain regions 70. The conductive silicide layers are formed by depositing a metal, such as cobalt or nickel over the semiconductor structure 98 and subsequently annealing the semiconductor structure 98 to react the metal with silicon in the source/drain region 70 and the gate conductor 52 to form metal silicide 72”, col. 5, line 66 to col. 6, line 6), the metal region is positioned in the first concave (lower half of 72 is in the equivalent concave of Wristers) and abuts against the heavily doped semiconductor region (72 abuts 70).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the first conductive region further comprising a metal region, the metal region is positioned in the first concave and abuts against the heavily doped semiconductor region.”, as disclosed by Wristers in the system of Yoshihara, for the purpose improving the contact interface to improve electrical flow across the boundary of metal conductor to the source/drain. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yoshihara et al. (US 2021/0167041) in view of Tanzawa (US 8,952,482) in view of Mori et al. (US 2009/0040850) in view of Hamaguchi (US 2006/0131657) in view of Chen et al. (US 11,562,923) in view of Liang et al. (US 6,071,783) in view of Holz et al. (US 2005/0280052).
Regarding claim 11, the prior art of Yoshihara et al. disclose the DRAM circuit in claim 1, however Yoshihara does not disclose, “wherein the horizontally extended isolation region is a composite isolation region.”
Holz discloses in Fig. 3G-3I, wherein the horizontally extended isolation region (8A, ¶ 0041, and 9, ¶ 0038) is a composite isolation region (as insulators in the final transistor in Fig. 3I, both 8A and 9 are electrically insulating features).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of, “wherein the horizontally extended isolation region is a composite isolation region.”, as disclosed by Holz in the system of Yoshihara, for the purpose improving the accuracy of the pattern creation of the isolation regions. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“12. The DRAM circuit in claim 11, wherein the composite isolation region includes an
oxide layer and a nitride layer over the oxide layer.”
Claims 14-18, 19 and 21-27 are allowed.
The following is an Examiner's statement of reasons for allowance: The complementary MOSFET structure, as recited in the claims of the instant invention fail to be taught by the prior art cited of interest.
Regarding claim 14, the prior art of Hamaguchi (US 2006/0131657) in Fig. 1, discloses a complementary MOSFET structure, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of semiconductor substate, array core circuit, sense amplifier, plurality of DRAM cells, peripheral circuit, the use of complementary MOSFET structure, planar P type MOSFET with source, drain, gate, planar N type MOSFET with source, drain, gate, localized isolation regions with horizontally extended isolation below the source and drain regions, lightly doped region, heavily doped region, access transistor, storage capacitor, and their relative orientations and electrical connections to each other, in conjunction with the limitations of,
“wherein the first source region or the first drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region laterally abutted against the lightly doped semiconductor region;
wherein one DRAM cell includes an access transistor and a storage capacitor, the access transistor comprises a third source region, a third drain region, and a third gate region, and the third source region or the third drain region includes a lightly doped semiconductor region and a heavily doped semiconductor region vertically abutted against the lightly doped semiconductor region.”
Regarding claim 19, the prior art of Hamaguchi (US 2006/0131657) in Fig. 1, discloses a complementary MOSFET structure, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of semiconductor substrate, array core circuit, sense amplifier, plurality of DRAM cells, access transistor, storage capacitor, peripheral circuit, planar P type MOSFET with selectively grown source and drain, planar N type MOSFET with selectively grown source and drain, localized isolation region includes horizontally extended isolation region, access transistor comprises source, drain, gate with portion under the semiconductor substrate surface, and their relative orientations and electrical connections to each other, in conjunction with the limitation of,
“wherein the first selectively grown source region or the first selectively grown drain
region includes a bottom surface lower than a bottom surface of the first gate region, and the third source region or the third drain region includes a bottom surface higher than a bottom surface of the third gate region.”
Regarding claim 22, the prior art of Hamaguchi (US 2006/0131657) in Fig. 1, discloses a complementary MOSFET structure, but fails to disclose the specific characteristic recited in the claims of the instant invention e.g. the combination of claimed features of a semiconductor substrate, planar P type MOSFET with first conductive region and gate region, planar N type MOSFET with second conductive region and gate region, localized isolation region, shallow trench isolation region, horizontally extended isolation region, and their relative orientation with respect to each other, in conjunction with the limitation of,
“wherein the first horizontally extended isolation region is a composite isolation region, and the composite isolation region includes an oxide layer and a nitride layer over the oxide layer.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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