DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang(USPGPUB DOCUMENT: 20050016948, hereinafter Yang) in view of FAn (USPGPUB DOCUMENT: 20210028310 hereinafter Fan) and Huang (USPGPUB DOCUMENT: 20200373246 hereinafter Huang).
Re claim 1 Yang discloses a manufacturing method of a semiconductor device, comprising: providing a semiconductor substrate(100); forming a hard mask over the semiconductor substrate(100); etching[0007] the semiconductor substrate(100) to form a first protrusion region and a plurality of second protrusion regions(protrusions between trench(103/104)es), wherein the first protrusion region is separated from a closest one of the second protrusion regions(protrusions between trench(103/104)es) by a first trench(103/104), and neighboring two of the second protrusion regions(protrusions between trench(103/104)es) are separated by a second trench(103/104); forming a first dielectric layer(105/106) lining the first trench(103/104) and the second trench(103/104); forming a second dielectric layer(105/106) in the first trench(103/104), wherein the second dielectric layer(105/106) is along the first dielectric layer(105/106) in the first trench(103/104); etching[0007] back the second dielectric layer(105/106) to form a blocking structure(109); and after etching[0007] back the second dielectric layer(105/106), filling the first trench(103/104) with a filling material(110), wherein the filling material(110) covers the blocking structure(109).
Yang does not disclose etching[0007] the semiconductor substrate(100) by using the hard mask as an etch mask; wherein the blocking structure includes a horizontal portion and two vertical portions extending upwards from opposite ends of the horizontal portion
Fan disclose etching the semiconductor substrate by using the hard mask as an etch mask [0041]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Yang in order to to enhance the performance of the semiconductor devices [0003, Yang]. In doing so, etching[0007 of Yang] the semiconductor substrate by using the hard mask as an etch mask [0041 of Fan]
Yang and Fan does not disclose wherein the blocking structure includes a horizontal portion and two vertical portions extending upwards from opposite ends of the horizontal portion
Huang disclose in Fig 1, rotate 180 degrees, wherein the blocking structure(105/114) includes a horizontal portion(horizontal portion of 105/114) and two vertical portions(vertical portions of 105/114) extending upwards from opposite ends of the horizontal portion
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Yang in order to to improve the quality, yield, and reliability [0002, Huang].
Re claim 2 Yang and FAn and Huang disclose the manufacturing method of claim 1, further comprising: forming a sacrificial layer over the second dielectric layer(105/106) and filling the first trench(103/104) with the sacrificial layer;performing a planarization process to the second dielectric layer(105/106) and the sacrificial layer, so that an upper surface of the second dielectric layer(105/106) and an upper surface of the sacrificial layer are leveled with an upper surface of the first dielectric layer(105/106); andafter etching[0007] back the second dielectric layer(105/106), removing the sacrificial layer.
Re claim 3 Yang and FAn and Huang disclose the manufacturing method of claim 2, wherein the filling material(110) and the first dielectric layer(105/106) are made of a first material, the second dielectric layer(105/106) is made of a second material, a dielectric constant of the first material is lower than a dielectric constant of the second material.
Re claim 4 Yang and FAn and Huang disclose the manufacturing method of claim 3, wherein the sacrificial layer is made of a third material, and the third material is differentfrom the second material.
Re claim 5 Yang and FAn and Huang disclose the manufacturing method of claim 1, wherein filling the first trench(103/104) with the filling material(110) comprises forming a filling material(110) layer over an upper surface of the first dielectric layer(105/106) and in the first trench(103/104); annealing the filling material(110) layer to cure the filling material(110) layer; and performing a chemical mechanical polish to remove a portion of the filling material(110) layer and the first dielectric layer(105/106), so that the hard mask is exposed and the filling material(110) is formed.
Re claim 6 Yang and FAn and Huang disclose the manufacturing method of claim 5, wherein the blocking structure(109) expands during annealing the filling material(110) layer and the filling material(110) layer shrinks during annealing the filling material(110) layer.
Re claim 7 Yang and FAn and Huang disclose the manufacturing method of claim 1, wherein etching[0007] back the blocking structure(109) is performed such that a top end of the blocking structure(109) is lower than a bottom of the hard mask and higher than upper surfaces of the second protrusion regions(protrusions between trench(103/104)es).
Re claim 8 Yang and FAn and Huang disclose the manufacturing method of claim 1, further comprising: forming an oxide layer at an upper surface of the semiconductor substrate(100) before forming the hard mask over the semiconductor substrate(100),wherein etching[0007] back the blocking structure(109) is performed such that a top end of the blocking structure(109) is lower than an upper surface of the oxide layer and higher than a bottom of the oxide layer.
Re claim 9 Yang and FAn and Huang disclose the manufacturing method of claim 1, wherein the first trench(103/104) is wider than the second trench(103/104).
Re claim 10 Yang discloses a manufacturing method of a semiconductor device, comprising: providing a semiconductor substrate(100); forming a hard mask over the semiconductor substrate(100); etching[0007] the semiconductor substrate(100) wherein the semiconductor substrate(100) is divided into a central region and a peripheral region, and the central region and the peripheral region are separated by a first trench(103/104);forming a first dielectric layer(105/106) along a sidewall of the semiconductor substrate(100) in the first trench(103/104); forming a blocking structure(109) in the first trench(103/104); andfilling the first trench(103/104) with a filling material(110), wherein the filling material(110) covers the blocking structure(109) and is in contact with the first dielectric layer(105/106).
Yang does not disclose etching[0007] the semiconductor substrate(100) by using the hard mask as an etch mask; wherein the blocking structure includes a horizontal portion and two vertical portions extending upwards from opposite ends of the horizontal portion
Fan disclose etching the semiconductor substrate by using the hard mask as an etch mask [0041]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Yang in order to to enhance the performance of the semiconductor devices [0003, Yang]. In doing so, etching[0007 of Yang] the semiconductor substrate by using the hard mask as an etch mask [0041 of Fan]
Yang and Fan does not disclose wherein the blocking structure includes a horizontal portion and two vertical portions extending upwards from opposite ends of the horizontal portion
Huang disclose in Fig 1, rotate 180 degrees, wherein the blocking structure(105/114) includes a horizontal portion(horizontal portion of 105/114) and two vertical portions (vertical portions of 105/114) extending upwards from opposite ends of the horizontal portion
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Yang in order to to improve the quality, yield, and reliability [0002, Huang].
Re claim 11 Yang and FAn and Huang disclose the manufacturing method of claim 10, further comprising: forming an oxide layer at an upper surface of the semiconductor substrate(100) before forming the hard mask over the semiconductor substrate(100).
Re claim 12 Yang and FAn and Huang disclose the manufacturing method of claim 11, wherein forming the blocking structure(109) in the first trench(103/104) comprises: forming a second dielectric layer(105/106) along the first dielectric layer(105/106); forming a sacrificial layer over the second dielectric layer(105/106) and filing the first trench(103/104);performing a planarization process to the second dielectric layer(105/106) and the sacrificial layer, so that an upper surface of the second dielectric layer(105/106) and anupper surface of the sacrificial layer are leveled with an upper surface of the first dielectric layer(105/106);etching[0007] the second dielectric layer(105/106), so that a top of the second dielectric layer(105/106) is lower than a bottom of the hard mask and higher than a bottom of the oxide layer, and the second dielectric layer(105/106) becomes the blocking structure(109);and removing the sacrificial layer.
Re claim 13 Yang and FAn and Huang disclose the manufacturing method of claim 10, wherein a flowable chemical vapor deposition is performed to fill the first trench(103/104) with the filling material(110).
Re claim 14 Yang and FAn and Huang disclose the manufacturing method of claim 13, wherein the filling material(110) and the first dielectric layer(105/106) are made of a first material, the blocking structure(109) is made of a second material, a dielectric constant of the first material is lower than a dielectric constant of the second material.
Re claim 15 Yang and FAn and Huang disclose the manufacturing method of claim 10, further comprising:removing the hard mask after filling the first trench(103/104) with the filling material(110).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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