DETAILED ACTION
This action is responsive to the application No. 18/204,081 filed on May 31, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/11/2026 with the associated claims filed on 02/24/2026 responding to the Office action mailed on 01/13/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 10-15 and 17-29.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 21, 22, and 24 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 21 recites “forming the liner structure 214 extending along sidewalls of the second fin structure 202 …”. However, as already established by claim 19, the liner structure 214 extends along sidewalls of the fin structure 204.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 11, 13-15, 17, 19, 20, and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang (US 2016/0181414).
Regarding Claim 10, Huang (see, e.g., Figs. 1-9), teaches a method for fabricating semiconductor devices, comprising:
forming a first fin structure 210 and a second fin structure 110 in a first region 200 and a second region 100 of a substrate 10, respectively, wherein the first 210 and second 110 fin structure and the substrate 10 comprise a first semiconductor material (see, e.g., Fig. 3, pars. 0013-0015);
forming a first liner structure 140 (i.e., left portion of 140 over fins 210) and a second liner structure 140 (i.e., right portion of 140 over fins 110) at least extending along sidewalls of the first fin structure 210 and sidewalls of the second fin structure 110, respectively, wherein the first liner structure 140 further overlays a first mask layer 345 defining the first fin structure 210, and the second liner structure 140 further overlays a second mask layer 345 defining the second fin structure 110 (see, e.g., Fig. 5, pars. 0019, 0028),
replacing an upper portion of the second fin structure 110 with a second semiconductor material 115, while leaving the first fin structure 210 substantially intact (see, e.g., Fig. 9, par. 0014); and
exposing a top surface and upper sidewalls of the first fin structure 210, and a top surface and upper sidewalls of the second fin structure 110 (see, e.g., Fig. 1, par. 0040).
Regarding Claim 11, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches that the exposed upper sidewalls of the first fin structure 210 are formed of the first semiconductor material, while the exposed upper sidewalls of the second fin structure 110 are formed of the second semiconductor material 115 (see, e.g., pars. 0014-0015).
Regarding Claim 13, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches:
forming a gate dielectric 121 over the first fin structure 210 and the second fin structure 110, respectively (see, e.g., par. 0021); and
forming a gate metal 220/110 over the first fin structure 210 and the second fin structure 110, respectively (see, e.g., par. 0021).
Regarding Claim 14, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches that the first fin structure 210 operatively serves as a conduction channel of an n-type field-effect-transistor, and the second fin structure 110 operatively serves as a conduction channel of a p-type field-effect-transistor (see, e.g., par. 0021).
Regarding Claim 15, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches that the first semiconductor material is silicon, and the second semiconductor material 115 is silicon germanium (see, e.g., par. 0014).
Regarding Claim 17, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches that the step of replacing an upper portion of the second fin structure 110 with a second semiconductor material 115, while leaving the first fin structure 210 substantially intact further comprises:
overlaying the first fin structure 210 and second fin structure 110 with an isolation structure 130 (see, e.g., Fig. 6, par. 0020);
covering the first region 200 (see, e.g., Fig. 8, par. 0037);
removing a portion of the isolation structure 130 in the second region 100, the second mask layer 345, and the upper portion of the second fin structure 110, while leaving the first region 100 substantially intact (see, e.g., Fig. 8); and
epitaxially growing, from a lower portion of the second fin structure 110, the second semiconductor material 115 as the replacement upper portion of the second fin structure 110 (see, e.g., Fig. 9, par. 0038).
Regarding Claim 19, Huang (see, e.g., Figs. 1-9), teaches a method for fabricating semiconductor devices, comprising:
forming a fin structure 110 protruding from a substrate 10, wherein the fin structure 210 and the substrate 10 comprise a first semiconductor material defined according to a mask layer 345 (see, e.g., Fig. 3, pars. 0013-0015, 0028);
forming a liner structure 140 extending along sidewalls of the fin structure 110 and overlaying the mask layer 345 over a top surface of the fin structure 110 (see, e.g., Fig. 5, pars. 0019, 0028),
removing a portion of the liner structure 140 overlaying the top surface, then the mask layer 345, and then an upper portion of the fin structure 110 (see, e.g., Figs. 7-8, pars. 0036-0037);
epitaxially growing, from a lower portion of the fin structure 110, a second semiconductor material 115 as a replacement upper portion of the fin structure 110, the second semiconductor material 115 being different from the first semiconductor material (see, e.g., Fig. 9, par. 0014);
exposing upper sidewalls of the fin structure 110 (see, e.g., Fig. 1, par. 0040); and
forming a gate structure 120 straddling the fin structure 110 (see, e.g., Fig. 1, par. 0021).
Regarding Claim 20, Huang teaches all aspects of claim 19. Huang (see, e.g., Figs. 1-9), teaches that the first semiconductor material is silicon, and the second semiconductor material 115 is silicon germanium (see, e.g., par. 0014).
Regarding Claim 23, Huang teaches all aspects of claim 10. Huang (see, e.g., Figs. 1-9), teaches that a different etch process used to remove each of:
an isolation material 130 formed over the first fin structure 210 and the second fin structure 110 (see, e.g., Fig. 6, par. 0020);
the second liner structure 140 and the second mask layer 345; and
the upper portion of the second fin structure 110.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2016/0181414) in view of Yu-Lien (US 2014/0239404).
Regarding Claim 12, Huang teaches all aspects of claim 10. Huang does not teach that the exposed upper sidewalls of the first fin structure have a first height and the exposed upper sidewalls of the second fin structure have a second height, the second height being greater than the first height.
Yu-Lien (see, e.g., Fig. 5B), in similar processes to Huang, on the other hand, teaches that the exposed upper sidewalls of the first fin structure 216/218 have a first height H2 and the exposed upper sidewalls of the second fin structure 212/214 have a second height H1, the second height H1 being greater than the first height H2. One advantageous feature of having different fin heights for NMOS transistors and PMOS transistor is that the threshold voltages of the NMOS transistors and the PMOS transistors may be tuned through adjusting the fin heights of the NMOS transistors and the PMOS transistors (see, e.g., par. 0038).
It would have been obvious to one of ordinary skill in the art at the time of filing to have in Huang’s process, the exposed upper sidewalls of the first fin structure having a first height and the exposed upper sidewalls of the second fin structure having a second height, the second height being greater than the first height, as taught by Yu-Lien, to tune the threshold voltages of the NMOS transistors and the PMOS transistors through adjusting the fin heights of the NMOS transistors and the PMOS transistors.
Regarding Claim 25, Huang (see, e.g., Figs. 1-9), teaches a method for fabricating semiconductor devices, comprising:
forming a first fin structure 210 and a second fin structure 110 in a first region 200 and a second region 100 of a substrate 10, respectively, wherein the first 210 and second 110 fin structure and the substrate 10 comprise a first semiconductor material (see, e.g., Fig. 3, pars. 0013-0015);
forming a first liner structure 140 (i.e., left portion of 140 over fins 210) and a second liner structure 140 (i.e., right portion of 140 over fins 110) at least extending along sidewalls of the first fin structure 210 and sidewalls of the second fin structure 110, respectively (see, e.g., Fig. 5, pars. 0019, 0028);
replacing an upper portion of the second fin structure 110 with a second semiconductor material 115, while leaving the first fin structure 210 substantially intact (see, e.g., Fig. 9, par. 0014);
exposing a first top surface and upper sidewalls of the first fin structure 210, and a second top surface and upper sidewalls of the second fin structure 110 (see, e.g., Fig. 1, par. 0040),
forming a first gate dielectric 121 over the first top surface and upper sidewalls of the first fin structure 210 (see, e.g., Fig. 1, par. 0021); and
forming a second gate dielectric 121 over the second top surface and upper sidewalls of the second fin structure 110 (see, e.g., Fig. 1, par. 0021).
Huang does not teach that the first top surface is of a first height, different from a second height of the second top surface.
Yu-Lien (see, e.g., Fig. 5B), in similar processes to Huang, on the other hand, teaches that the first top surface is of a first height H2, different from a second height H1 of the second top surface. One advantageous feature of having different fin heights for NMOS transistors and PMOS transistor is that the threshold voltages of the NMOS transistors and the PMOS transistors may be tuned through adjusting the fin heights of the NMOS transistors and the PMOS transistors (see, e.g., par. 0038).
It would have been obvious to one of ordinary skill in the art at the time of filing to have in Huang’s process, the first top surface being of a first height, different from a second height of the second top surface, as taught by Yu-Lien, to tune the threshold voltages of the NMOS transistors and the PMOS transistors through adjusting the fin heights of the NMOS transistors and the PMOS transistors.
Claims 21, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US 2016/0181414) in view of Yu (US 2020/0212037).
Regarding Claim 21, Huang teaches all aspects of claim 19. Huang (see, e.g., Figs. 1-9), teaches that the method further comprises:
forming a second fin structure 210 protruding from the substrate 10, wherein the second fin structure 210 and the substrate 10 comprise the first semiconductor material defined according to a second mask layer 345 (see, e.g., Fig. 3, pars. 0013-0015, 0028);
forming the liner structure 140 extending along sidewalls of the second fin structure 210 and overlaying the second mask layer 345 over a top surface of the second fin structure 210 (see, e.g., Fig. 5, pars. 0019, 0028);
removing a portion of the liner structure 140 overlaying the top surface of the second fin structure 210, and then the second mask layer 345 (see, e.g., Fig. 7, par. 0036);
exposing upper sidewalls of the second fin structure 210 (see, e.g., Fig. 1, par. 0040); and
forming a second gate structure 220 straddling the second fin structure 210 (see, e.g., Fig. 1, par. 0021).
Huang does not teach that an upper surface of a gate dielectric of the second gate structure is lower than an upper surface of a gate dielectric of the gate structure.
Yu (see, e.g., Fig. 4), in similar processes to Huang, on the other hand, teaches that an upper surface of a gate dielectric 24L of the second gate structure 26L is lower than an upper surface of a gate dielectric 24R of the gate structure 26R, to achieve a semiconductor structure including a first FinFET device FS1 for low power applications and a second FinFET device FS2 for non-low power applications. The first FinFET device FS1 has an active fin height h3, i.e., channel height, which is less that an active fin height h4 of the second FinFET device FS2 (see, e.g., pars. 0005, 0046).
It would have been obvious to one of ordinary skill in the art at the time of filing to include in Huang’s process, an upper surface of a gate dielectric of the second gate structure being lower than an upper surface of a gate dielectric of the gate structure, as taught by Yu, to achieve a semiconductor structure including a first FinFET device for low power applications and a second FinFET device for non-low power applications.
Regarding Claim 22, Huang and Yu teach all aspects of claim 21. Huang (see, e.g., Figs. 1-9), teaches that the first fin structure 210 operatively serves as a conduction channel of one of an n-type field-effect-transistor (FET) or a p-type FET, and the second fin structure 110 operatively serves as the other of the n-type FET or the p-type FET (see, e.g., par. 0021).
Regarding Claim 24, Huang and Yu teach all aspects of claim 21. Huang (see, e.g., Figs. 1-9), teaches that a different etch process used to remove each of:
an isolation material 130 formed over the fin structure 110 and the second fin structure 210 (see, e.g., par. 0036);
the liner structure 140 (see, e.g., par. 0037); and
the upper portion of the fin structure 110 (see, e.g., par. 0037).
Allowable Subject Matter
Claims 18 and 26-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Garcés whose telephone number is (571)272-8249. The examiner can normally be reached on M-F 9:00 AM - 5:00 PM.
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/Nelson Garces/Primary Examiner, Art Unit 2814
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