Prosecution Insights
Last updated: April 18, 2026
Application No. 18/204,398

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Non-Final OA §103
Filed
Jun 01, 2023
Examiner
PETERSON, ERIK T
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
UNITED MICROELECTRONICS CORPORATION
OA Round
5 (Non-Final)
77%
Grant Probability
Favorable
5-6
OA Rounds
2y 8m
To Grant
89%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
271 granted / 353 resolved
+8.8% vs TC avg
Moderate +12% lift
Without
With
+12.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
40 currently pending
Career history
393
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
39.3%
-0.7% vs TC avg
§102
24.7%
-15.3% vs TC avg
§112
29.7%
-10.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 353 resolved cases

Office Action

§103
DETAILED ACTION This action is responsive to the amendment received December 16, 2025. The amendment has been entered. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Shariff et al. (US 2013/0178413, of record) in view of Grivna et al. (US 2010/0120230, newly cited). (Re Claim 7) Shariff teaches a semiconductor device, comprising (see Fig. 2c and ¶40): a chip obtained after a dicing process (Fig. 2c), wherein the chip comprises a wafer (wafer 210), and the wafer comprises: a first sidewall comprising a top portion and a bottom portion, wherein the top portion comprises a first profile, the bottom portion comprises a second profile, and the first profile and the second profile are different, wherein the first profile comprises a scallop shape surface intersecting a top surface of the wafer (upper portion of 210), the second profile comprises a planar surface (lower portion of 210 at BU); a second sidewall comprising a second top portion and a second bottom portion, wherein the second top portion comprises a third profile, the second bottom portion comprises a fourth profile, and the third profile and the fourth profile are different, wherein the third profile comprises a scallop shape surface intersecting the top surface of the wafer, the fourth profile comprises a planar surface, and wherein the top portion, the bottom portion, the second top portion and the second bottom portion comprise the same material (Fig. 2c). Regarding wherein a thickness of the bottom portion is 5% or less of a thickness of the top portion, and the thickness of the bottom portion ranges from 5 to 10 microns, Shariff teaches the bottom portion (flat planar BU portion of 210) is 5% of the wafer thickness (¶40), however Shariff does not teach a thickness of the wafer. A PHOSITA would be motivated to look to related art to teach suitable wafer thicknesses for conventional semiconductor devices. Related art from Grivna discloses a wafer thickness of about 100-200 microns (¶27) and/or about 50-250 microns (¶58). In light of Grivna’s conventional wafer thickness(es) applied to Shariff’s wafer, since Shariff is silent on the thickness, for a bottom portion thickness being 5% of the top portion thickness and wherein the bottom portion is 5-10 µm, this requires a wafer thickness in a range of about 105-210 µm. Grivna teaches a wafer thickness of about1 100-200 µm and/or a thickness of about 50-250 µm, thus when using a wafer thickness according to Grivna’s thickness ranges in Shariff’s BU being 5% of the wafer thickness, one will naturally arrive at the claimed thickness of the bottom portion being 5% or less of a thickness of the top portion, and the thickness of the bottom portion ranges from 5 to 10 microns (e.g. for a ~105 µm thick wafer, 5% of the thickness is ~5.25 µm which is within the claimed range for the bottom portion thickness). Thus the claimed bottom portion thickness range would be obvious to a PHOSITA as this would flow naturally from selecting a known wafer thickness according to Grivna for Shariff’s wafer thickness in conjunction with the 5% BU thickness ratio. Furthermore, the specification contains no disclosure of either the critical nature of the claimed thickness nor any unexpected results arising therefrom. "The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. . . . In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range." In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). Response to Arguments Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898 1 “about” includes values slightly above and below, e.g. 105 microns is understood to be included in the about 100 microns just as about 200 microns includes 210 microns.
Read full office action

Prosecution Timeline

Jun 01, 2023
Application Filed
Aug 18, 2025
Non-Final Rejection — §103
Sep 24, 2025
Response Filed
Sep 30, 2025
Final Rejection — §103
Nov 07, 2025
Request for Continued Examination
Nov 14, 2025
Response after Non-Final Action
Nov 19, 2025
Non-Final Rejection — §103
Dec 16, 2025
Response Filed
Jan 05, 2026
Final Rejection — §103
Mar 02, 2026
Interview Requested
Mar 11, 2026
Examiner Interview Summary
Mar 11, 2026
Applicant Interview (Telephonic)
Mar 31, 2026
Request for Continued Examination
Apr 08, 2026
Response after Non-Final Action
Apr 10, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Semiconductor Device and Method of Manufacture
2y 5m to grant Granted Mar 31, 2026
Patent 12591325
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Patent 12575374
METHOD OF PREPARING A STRUCTURED SUBSTRATE FOR DIRECT BONDING
2y 5m to grant Granted Mar 10, 2026
Patent 12568750
DISPLAY PANEL AND DISPLAY DEVICE
2y 5m to grant Granted Mar 03, 2026
Patent 12564068
Carbon Assisted Semiconductor Dicing And Method
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
77%
Grant Probability
89%
With Interview (+12.0%)
2y 8m
Median Time to Grant
High
PTA Risk
Based on 353 resolved cases by this examiner. Grant probability derived from career allow rate.

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