DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-5) / Species A (Fig. 5) in the reply filed on 9/25/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2012/0113376 (Hayashi, cited by Applicant) in view of U.S. Patent Application Publication No. 2020/0333909 (Chen).
Hayashi discloses (at least Figs. 1-16)
1. (Currently Amended) A wiring substrate comprising:
a first terminal 48a1 or 48b1;
a second terminal 48a2 or 48b2 disposed side by side at an interval from the first terminal in a first direction;
a third terminal 49a or 49b disposed side by side at an interval from the first terminal in the first direction on a side opposite the second terminal;
a first wiring 43 positioned between the first terminal and the second terminal, and extending along a second direction intersecting the first direction;
a second wiring 44 connected to the first terminal and the third terminal; and
an insulating portion 9 disposed on an upper layer side of the first terminal, the second terminal, the third terminal, the first wiring, and the second wiring.
Hayashi fails to disclose
wherein the third terminal is further disposed at a position where an interval between the third terminal and the first terminal is longer than any of an interval between the first wiring and the first terminal and an interval between the first wiring and the second terminal.
Chen teaches (at least Figs. 7A-7D)
A wiring substrate comprising:
wherein the third terminal BP1 (1st row, 2nd column from the left in Fig. 7C) is further disposed at a position where an interval between the third terminal and the first terminal BP1 (1st row, 3rd column from the left in Fig. 7C) is longer than any of an interval between the first wiring DL and the first terminal and an interval between the first wiring DL and the second terminal BPR1 (1st row, 3rd column from the right in Fig. 7C).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to arrange the terminal and wirings as based on engineering design considerations in Hayashi. The motivation would be to reduce the difference in signal transmission or RC loading as taught by Chen ([0005]-[0009], [0032]-[0034], [0076]). See MPEP 2144.04.
Chen teaches
2. (Currently Amended) The wiring substrate according to claim 1, further comprising:
a fourth terminal BPR2 (3rd row, 3rd column from left in Fig. 7C) disposed at an interval from the first terminal in the second direction;
a fifth terminal BPR2 (2nd row, 2nd column from right in Fig. 7C) disposed at an interval from the second terminal in the second direction, and disposed side by side at an interval from the fourth terminal in the first direction; and
a sixth terminal BPR2 (4th row, 3rd column from left in Fig. 7C) disposed at an interval from the third terminal in the second direction, and disposed side by side at an interval from the fourth terminal in the first direction on a side opposite the fifth terminal, wherein:
mounted components 118 are mounted on positions of the wiring substrate that overlap with at least the first terminal, the second terminal, the third terminal, the fourth terminal, the fifth terminal, and the sixth terminal, and
the first terminal BP1 (1st row, 3rd column from left), the second terminal BPR1 (1st row, 3rd column from right), and the third terminal BP1 (1st row, 2nd column from the left) are positioned closer to an end of the mounted components 118 than the fourth terminal BPR2 (3rd row, 3rd column from left), the fifth terminal BPR2 (2nd row, 2nd column from right), and the sixth terminal BP3 (4th row, 3rd column from left).
Chen teaches
3. (Currently Amended) The wiring substrate according to claim 2, further comprising:
a third wiring DL3 connected to the third terminal and the sixth terminal.
Chen teaches
4. (Currently Amended) The wiring substrate according to claim 2, further comprising:
a fourth wiring DL connected to the fourth terminal and the sixth terminal.
Chen teaches
5. (Currently Amended) The wiring substrate according to claim 4, wherein
the sixth terminal BPR2 (4th row, 3rd column from left) is further disposed at a position where an interval between the sixth terminal BPR2 (4th row, 3rd column from left) and the third terminal BP3 (1st row, 2nd column from the left) in the second direction is longer than any of an interval between the first terminal BP1 (1st row, 3rd column from left) and the fourth terminal BPR2 (3rd row, 3rd column from left) in the second direction and an interval between the second terminal BPR1 (1st row, 3rd column from right) and the fifth terminal BPR2 (2nd row, 2nd column from right) in the second direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP Publication No. 2019-159240 (Kuroe), U.S. Patent Application Publication Nos. 2007/0030409 (Aoki), 2019/0137835 (Akiyama), 2022/0327857 (Kusunoki) teach a wiring substrate having multiple terminals and wirings.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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